FTM signal start conditions

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FTM signal start conditions

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frankschuetz
Contributor I

Hello,

I have written an driver that generates 2 digital signals with FTM.

Blue signal has a frequency with 1.6 MHz and is generated with FTM0.

Red signal has a frequency with 750 Hz and is generated with FTM1.

Both FTM instances are synchronized with the global time base (GTB).

So it works fine.

But there is a problem on starting signals (picture below).

FTM_Signals_starting.png

The blue signal should be start (user defined time) earlier as the red signal!

I have tried a lot, e.g. start PWM instance (FTM1) for red signal later (with sleep 1msec) as the blue signal on FTM0.

Or enable the specified channel later...

But the main problem is the enabling of GTB, because the signals are switched on (almost) simultaneously if GTB is enabled (so as in the picture above).

And if the GTB is enabled then some register values can no more be written because there are locked.

Is there a way to solve this problem?

Thanks in advance!

Here is a code snippet:

    FTM_HAL_SetGlobalTimeBaseCmd(FTM0, true);   //enable FTM0 GTBEEN

    FTM_HAL_SetGlobalTimeBaseCmd(FTM3, true);   //enable FTM3 GTBEEN

    FTM_DRV_PwmStart(BOARD_FTM0_INSTANCE);

    FTM_DRV_PwmStart(BOARD_FTM3_INSTANCE);

    FTM_HAL_SetCounter(FTM0, 0000U);        //clear FTM0 counter value to 0

    FTM_HAL_SetCounter(FTM3, 0000U);        //clear FTM3 counter value to 0

    FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM0, true);      //Enable FTM0 GTBEOUT

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Frank,

I think it is okay to have blue signal appear before the rising edge of red signal. This is my idea. As you know that the FTM0/FTM1 counter will start simultaneously with the global time base (GTB), we can use the different mode to implement that the blue signal appear before the red signal.

we can set both FTM0/FTM1 in edge alignment mode, while set the blue signal(FTM0) in edge-alignment and High-true pulses(clear Output on match) mode, in this way, the blue signal will rise when the FTM0 counter is zero. Pls refer to section 42.3.6 Channel (n) Status And Control (FTMx_CnSC) in RM of Kinetis.

we can set the red signal(FTM1) in edge-alignment, low-true pulses(set output on match) and combined mode, in combined mode, the red signal waveform is low-High-low, the rising edge instant is controlled by C0V register, the falling edge is controlled by C1V register if the red signal is outputted from FTM1_CH0. in this way, if we set appropriate value for the FTM1_C0V(the delay clock number),  the blue signal will appear before the red signal although the FTM0/FTM1 synchronize.

Note that if you use combined mode, the FTM1_CH0/FTM1_CH1 should be in complementary mode.

Hope it can help you.

BR

Xiangjun Rong

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frankschuetz
Contributor I

Hello Xiangjun,

I have an additional question to FTM. I want to use the FTM synchronization mode to update the FTM counter value to CNTIN register value on synchronization event. I have set up a FTM3 channel 2 to generate a signal (like the blue signal above, e.g. 1KHz, square wave, 50% duty cycle). There is an input signal that is connected to the pin FTM3_FLT0 (FTM3 hardware trigger 2). This input signal should influence the FTM counter value that the output signal is also influenced and will get another duty cycle.

Unfortunately, it doesn't work! The test input signal is has 1500Hz, 50% duty cycle and square wave.

Is something not complete for the FTM3 setup or is my imagination wrong?

For pin FTM3_FLT0, I have setup the PTC12 and PTD12 with ALT6. The input signal was connected to TWR-K65F180 on extension plug (C43, B77 and B48). But nothing happens.

Here are 2 screenshots that shows the FTM3 configuration:

TWR-K65F180M_FTM3_part1.png

TWR-K65F180M_FTM3_part2.png

Thanks in advance!

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Frank,

Of course, as you said that the FTM supports external triggering mode, the rising edge of external signal can initialize the FTM _CNT counter to FTM_CNTIN register, PWM waveform will start. Regarding the register setting of the mode, I suggest you refer to  section 3.11.4. Updating the FTM register with hardware control in an5142(Features of the FlexTimer Module) which can be downloaded from the website:

K40_100 |Kinetis K40 100 MHz MCUs|NXP

you can refer to the code to implement the hardware triggering.

for example, for the pin assignment, if you want to set the PTC12 as FTM3_FLT0, you should enable the PORTC gate clock by setting the PORTC bit in SIM_SCGC5, set the MUX bits of the PORTC_PCR12 as ALT6.

FTM0_SYNC|=0x40;

FTM0_SYNCONF|=0x30001; //HWWRBUF=1: MOD, CnV all updated by hardware triggering, HWRSTCNT=1: FTM0 counter count from CNTIN register value

Hope it can help you.

BR

Xiangjun Rong

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651 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Frank,

I think it is okay to have blue signal appear before the rising edge of red signal. This is my idea. As you know that the FTM0/FTM1 counter will start simultaneously with the global time base (GTB), we can use the different mode to implement that the blue signal appear before the red signal.

we can set both FTM0/FTM1 in edge alignment mode, while set the blue signal(FTM0) in edge-alignment and High-true pulses(clear Output on match) mode, in this way, the blue signal will rise when the FTM0 counter is zero. Pls refer to section 42.3.6 Channel (n) Status And Control (FTMx_CnSC) in RM of Kinetis.

we can set the red signal(FTM1) in edge-alignment, low-true pulses(set output on match) and combined mode, in combined mode, the red signal waveform is low-High-low, the rising edge instant is controlled by C0V register, the falling edge is controlled by C1V register if the red signal is outputted from FTM1_CH0. in this way, if we set appropriate value for the FTM1_C0V(the delay clock number),  the blue signal will appear before the red signal although the FTM0/FTM1 synchronize.

Note that if you use combined mode, the FTM1_CH0/FTM1_CH1 should be in complementary mode.

Hope it can help you.

BR

Xiangjun Rong

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