Does NXP have any requirements in time for SOFTRST/FRZACK/LPMACK of CANx_MCR? (Vybrid_F Series)

[norihiromichiga]

Hello NXP team,

Please let me ask you if CANx_MCR has requirement of wait time.

I believe following bits in CANx_MCR is status bits that allow me to confirm the hardware is in expected state.

  Field = bit25(SOFTRST)

  Field = bit24(FRZACK)

  Field = bit20(LPMACK)

Does NXP have any requirements of "wait time" or "number of polling" for these bits?

For example,  when I want to put your device in low-power mode of FlexCAN, I usually wait LPMACK bit changes to "1".

In this case, do you have requirements for wait time before reading this bit or the number of polling of this bit?

In your reference code, we can find below. It waits until the status bit changes.

If I check the status of both configuration mode & mode setting like below, I can expect that bit20(LPMACK) must be changed?

I'm worrying that if the condition of (CAN1_MCR & CAN_MCR_LPMACK_MASK) stays at "0",  program counter stays at this point forever.

Or,  we must set the limitation in the time (or number of polling) when I read this bit?

This is slightly urgent question, so your timely response is very appreciated.

  ------------------------------------------------------

          /* clock disable (module) */

          CAN1_MCR = CAN_MCR_MDIS_MASK;

          /* wait until disable mode acknowledged */

          while (!(CAN1_MCR & CAN_MCR_LPMACK_MASK)) {}

  ------------------------------------------------------

Thanks,

Norihiro Michigami

AVNET

[alejandrolozan1]

Hi,

According to the RM the time you will have to wait for the FlexCAN module goes out of Low powe mode will be dependant on the bit CAN timing.

LPMACK will be asserted within 180 CAN bits from the low-power mode request by the CPU, and

negated within 2 CAN bits after the low-power mode request removal.

Therefore if you already know the period of the CAN bit  you can calculate the time of the 180 bit cycles when going to LPM or 2 when exit. I would increase this time in case a transmission or reception process is in progress.

Best Regards,

Alejandro

[soichiyamamoto]

Hi,

How about afterwards?

I hurry an answer.

I would like escalation again.

Best regards,

Soichi

[alejandrolozan1]

Hi Soichi,

The experts are already handling this. Thanks for your patiance.

I will get back to you as soon as possible.

Best Regards,

Alejandro

[alejandrolozan1]

Hi,

Sorry for the delay.

it should take couple of clocks - asked designers.

Also there will be some propagation time - registers works on IPS_bus clock and FlexCAN on its clock.

Also write into the resister takes some time (request have to pass NIC and AIPS)

Do not know about any limitation for number of pooling.

The soft reset starts just after the write into MCR. The flip-flops which are on the CHI (Controller Host Interface) clock domain are reset just after the write into MCR. The flip-flops which are on the PE (Protocol Engine) clock domain are not reset immediately because of the clock domain interface latency between CHI and PE. So that the soft reset request crosses the clock domain interface from CHI to PE, it takes up to 1 CAN bit (worst case).

SOFTRST bit can be checked immediately since the bit has already been set after the MCR write operation.

SOFTRST bit remains set until the process of soft reset has been finished on both clock domain (PE and CHI).

To finish soft reset it takes (in the worst case) 1 CAN bit + 4 PE clock period + 4 CHI clock period (around 2 nominal CAN bits for sake of simplicity).  After resetting the flops on PE side, it takes 4 PE clock period + 4 CHI clock period so that the CHI receives an acknowledge signal and clears the SOFTRST bit.

I hope that helps.

Alejandro

[soichiyamamoto]

Hi,

Thank you.

When the following field becomes active, please tell the maximum of the time-out.

Field = bit25(SOFTRST)

Field = bit24(FRZACK)

Does NXP have any requirements of "wait time" or "number of polling" for these bits?

Because this hurries very much, I would like cooperation.

Best regards.

soichi

[alejandrolozan1]

Hi,

FRZACK will be asserted within 178 CAN bits from the freeze mode request by the CPU, and

negated within 2 CAN bits after the freeze mode request removal (see Section "Protocol Timing").

Regarding the SFTRST, I will have to contact the designers.

Best Regards,

Alejandro

[soichiyamamoto]

Hi,

Thank you.

I add a question.

Module Configuration Register (CANx_MCR)

Field = bit25(SOFTRST)

Field = bit24(FRZACK)

Field = bit20(LPMACK)

When CAN bus is busy, Does the active time of the above-mentioned bit fluctuate?

Best Regards,

soichi