AnsweredAssumed Answered

Does NXP have any requirements in time for SOFTRST/FRZACK/LPMACK of CANx_MCR? (Vybrid_F Series)

Question asked by Norihiro Michigami on Feb 24, 2016
Latest reply on Mar 9, 2016 by alejandrolozano

Hello NXP team,

Please let me ask you if CANx_MCR has requirement of wait time.

I believe following bits in CANx_MCR is status bits that allow me to confirm the hardware is in expected state.

  Field = bit25(SOFTRST)

  Field = bit24(FRZACK)

  Field = bit20(LPMACK)

Does NXP have any requirements of "wait time" or "number of polling" for these bits?

For example,  when I want to put your device in low-power mode of FlexCAN, I usually wait LPMACK bit changes to "1".

In this case, do you have requirements for wait time before reading this bit or the number of polling of this bit?

In your reference code, we can find below. It waits until the status bit changes.

If I check the status of both configuration mode & mode setting like below, I can expect that bit20(LPMACK) must be changed?

I'm worrying that if the condition of (CAN1_MCR & CAN_MCR_LPMACK_MASK) stays at "0",  program counter stays at this point forever.

Or,  we must set the limitation in the time (or number of polling) when I read this bit?

This is slightly urgent question, so your timely response is very appreciated.

  ------------------------------------------------------

          /* clock disable (module) */

          CAN1_MCR = CAN_MCR_MDIS_MASK;

          /* wait until disable mode acknowledged */

          while (!(CAN1_MCR & CAN_MCR_LPMACK_MASK)) {}

  ------------------------------------------------------

Thanks,

Norihiro Michigami

AVNET

Outcomes