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8-bit data width DDR3 on iMX6DL

Question asked by Steven Barker on Feb 24, 2016
Latest reply on Feb 24, 2016 by igorpadykov

I have designed a board that uses a single 8Gb (1GB) DDR3 chip (MT41K1G8S-125) and assumed that if you only used x8 you just use the lower dqs0/d[0:7] and it should be fine. However now that I've had the device made, in testing I have found that isn't the case and the 8 most significant bits are lost into the non-existent upper 8-bits for every write to RAM. I've had a look through the reference manual but is there any register settings that I have missed that would allow this device to work, at least for testing purposes while I work on my next design to fix it (Going to change to the MT41K512M16 variant) for future runs.

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