I am designing a board with SGTL5000 for the audio codec. I currently have connected an external 24MHz clock directly to the codec to provide the SYS_MCLK signal.
When playing audio for periods the quality is very good but then for periods I get a lot of noise and the the audio seems to switch rapidly between left and right channels.
Must the SYS_MCLK signal be synchronous (generated by the cpu) to the CPU's clocks? Currently I imagine something is drifting in and out of sync.
How accurate must the CLK actually be?
I am trying to find another suitable clock available on my board to test this.