I'm working with i.MX6 connected to 2 codecs through SS1 & SS2 in I2S master mode.
Both of their clocks are originated from PLL4 (688.128 MHz), their SSI's sys clocks = 12.288 MHz, and their serial BCLKs = 1.536 MHz.
I wanted to connect the codecs' MCLKs, through CPLD, to SSI1_CLK and SSI2_CLK.
Both SSIx_CLKs can be routed to CLKO2 (by setting CCM_CCOSR accordingly) but not simultaneously.
On the other hand, connecting both MCLKs to the same SSIx_CLK causes phase shift problems in the codecs.
So I figured I'll connect the second MCLK through CPLD to the respective network clock (SRCK), which is AUD4_RXC.
In order to do that I set both TXDIR and SYS_CLK_EN to 1 (in SSI2_STCR and SSI2_SCR registers), but nothing appeared on AUD4_RXC (please refer to Figure 61-22 in i.MX6 RM).
Any suggestions why?
i.e. I've set DISP0_DAT19 pin in IOMUX to AUD4_RXC instead of GPIO_5_13 (PCIE_RST).
And I also set that pad to CMOS output:
|__raw_writel(0x1F0F1, IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19);||// PU=22K, Open Drain disabled (CMOS output), Speed=Max|