Ref: Doc MPC8641DCE, Rev 1, dtd 07/2009.
Page 120, PEX #18.
The eratta is "silent" with respect to which PCIe ports it is applicable to, whether Root Complex, EndPoint, or both.
Does the eratta apply to Root Complex Only? or, said a different way, does it apply to only the ports that the processor is "master" of (ie: The processor asserts reset on only the RC ports)
Because, if it also applies to End Points, then how does the End Point notify (signal) the bus master that the Endpoint is about to assert a reset on it's end?
In our system, interrupts / exceptions are not enabled during this initialization time, therefore an inbound interrupt signalling event of a port "going down", is not signalled to the processor.