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Defect in KDS Processor Expert on FC1 TImers( circumstance of two divided-frequency )

Question asked by Yu Jin on Feb 22, 2016
Latest reply on Feb 22, 2016 by Alice_Yang

when I set a FC1 TImers(FreeControl Timer) of 2.5ms(10ms,or5ms), the result will not correspond with my setting.

And  i found the reason is that there is  something wrong with the code in function TU1_Init() , the bit of the register that set the number which the timer clock should be divided into turns 0(actually it should be 1—two divided-frequency).