Expected value of MCSR in MPC8548E after PCI parity error

[dallasclow]

Our system uses an MPC8548E with a PCIe/PCI-X bridge attached to the MPC8548E PCIe interface.  A PCI device is attached to the PCI-X side of the bridge.  Our customer would like to customize the machine check handler for the MPC8548E and would like to know what the expected value of the Machine Check Syndrome Register (MCSR) is if the PCI device produces a parity error during a target read transaction (PCIe/PCI-X bridge is the master for a read generated originally by the MPC8548E).  This isn't clear from the reference manual.  I've also reviewed the EIS and e500 core manuals and didn't see answers there.  Is there additional documentation or can this question be answered directly?

[alexander_yakov]

Assuming this transaction is generated by e500 core bus master, from the core point of view the result should similar to one described in Table 5-10 of e500 core reference manual, as the e500 core is unaware which bus target it is accessing.

Have a great day,
Alexander

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[dallasclow]

Will the parity error on the PCI-X bus propagate and be reported as BUS_RPERR or not propagated and reported as BUS_RBERR?