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SDMA Event Mapping controlling register bit selection

Question asked by Yee Lun Ong on Feb 21, 2016
Latest reply on Mar 16, 2016 by Victor Linnik

For i.MX6 solo/dualite's SDMA event mapping, for instance,


SDMA Event number 23 (ESAI/I2C3) 's description came with muxing description with respect to GPR0[6] IOMUXC register. When dive into IOMUXC_GPR0[6] register, the bit selection for muxing sources is straight and clear.


However, for SDMA Event number 29 (UART3/QSPI1) and 30(UART3.QSPI2), the controlling register (GPR0[21], GPR0[22]) bit selection description are not as clear as what had been described in SDMA event number 23.


Is there's any documentation/information providing insight into IOMUXC_GPR0 register's GPR0[21], GPR0[22] bit field?


Thank you.


~ Y.L