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MC56F84xxx DSC 32 bit transfers

Question asked by Jeff Dottor Employee on Feb 22, 2016
Latest reply on Feb 24, 2016 by Fiona Kuang

Please explain the behavior of the post increment register when loading 32 bit numbers to either Y or an accumulator.

 

I am using these two instructions with the number 7 in the N register. I have 0x87ff in M01 which causes modulo addressing in both R0 and R1.

 

tfr    A,B       X:(R0)+N,C

mpy32   C,Y,A    X:(R1)+N,C

 

When executing the first instruction the R0 register increments by 7. When executing the second instruction the R1 register increments by 14. Either is logical. Incrementing by 14 is logical because there are two addresses per long transfer to C. I can either double N or not depending on the correct behavior. But I can't use both of these instructions in the same DSP loop as the N register is treated differently in the two cases.

 

Can you please tell me why the DSP works this way and if this is correct and most important, where can I find this documented in the DSP56800ERM manual. The 32 bit parallel loads are mentioned scantily in section A.3. Other places the only reference are to 16 bit moves, not 32 bit moves.

 

After further work I understand part of the problem. The issues are probably only with documentation.

 

The first instruction moves only 16 bits so it's logical to increment R0 by 7.

The second instruction moves 32 bits so bumping R1 by 14 is logical too.

 

In table 4-49 the documentation says that all parallel moves are 16 bits. But this is not true. The second instruction does in fact move 32 bits. That may be because those instructions are only EX. But please explain to me the difference in table 4-49 between

 

X:(R0)+N,A

X:(R0)+N,A1

 

Is it sign extension? I don't see any reason for the difference.

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