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Leak voltage to USB_OTG_DP / N during the reset.

Question asked by Takashi Takahashi on Feb 21, 2016
Latest reply on Feb 21, 2016 by igorpadykov

Hi community.

 

Our customer has question below.

To ask  about the leak voltage to USB_OTG_DP / N during the reset.

Please see atached Fig.

Currently, leak voltage will have occurred  from the outside, on the system (actual device) USB_OTG_DP / N.

Leak voltage is about 0.3V, but we are concerned about the latch-up and reverse current flow occurs because it has been applied to the PowerSpurce (USB_OTG_VBUS and VDDUSB_CAP) before the launch of the USB_OTG_DP / N.

Would you please advice to me, Is it necessary for the latch-up and the current back-flow measures or accepable range .

 

Thasnks,

Best.

T.Takahashi

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