I use the TWR-K65F180M with KSDK 1.3.0 and KDS 3.0.0.
I have developed successfully a software driver that we can capture a run length of a digital signal. There is a FTM counter for counting the run length and there is a set up of 2 eDMA channels to capture the counting values. There are 2 buffers, one for rising edges and one for falling edges. Each buffer is written by a eDMA channel. If the buffer is complete a DMA ISR is occurred and the counting values can be processed further.
So far so good.
Now, there is a new requirement:
If a high phase of this run length signal is greater than a fix specified value then a digital output must be switch on immediately.
The CPU may not be occurred!
My question is now:
How can I implement this feature?
My idea #1:
It is possible to configure the eDMA channel in this way that the FTM2 counter will be reset on each minor loop? So I could configure maximum counter value of FTM2 counter to the fixed value. And if the counter is overflowed then an interrupt will be generated to set a digital output.
My idea #2 (maybe the better way):
A new instance or FTM is set up (i.e. FTM3) to generate the digital output signal. The counter value of this instance must be reset every time by a positive edge of the captured run length signal and specified fix value will be write into a specified FTM3 register. If the counter value is grater than the fix value then the FTM3 set the output to high. I don't know if it is possible in this way.
Do you have a better idea?
If you have a solution, please can you give me an example?
Thanks in advance!