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Unexpected UART_RTS_B interrupt on i.MX6UL

Question asked by yuuki on Feb 18, 2016
Latest reply on Mar 15, 2016 by gusarambula

Dear all,

 

We have a problem that RTS_B interrupt occurs though UART6 is not used.

 

CPU is i.MX6UL.

BSP is L3.14.52_1.1.0-ga

 

In IOMUX, the UART6_RTS_B signal is assigned to CSI_VSYNC pin(ALT8) and ENET1_TX_EN pin(ALT1).

However, CSI_VSYNC pin is used as ALT1:USDHC2_CLK and ENET_TX_EN pin is used as ALT0:ENET_TX_EN.

 

<Register Seting>

- IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN 0x020E00D8  0x00000000

- IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC   0x020E01DC  0x00000001

 

When a clock is input into CSI_VSINC pin, an interrupt of UART_RTS_B occurs.

It seems that a signal from CSI_VSYNC pin is entered in RTS of UART port.

 

IOMUXC_UART6_RTS_B_SELECT_INPUT register remains a default value

(0x00000000 :CSI_VSYNC_ALT8 => UART6_RTS_B)

 

Would you tell me the method to disable RTS_B interrupt?

 

Best Regards,

Yuuki

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