Regarding to PGA concept, I have 2 analog signals output from the Low Pass Filter Circuits . These 2 signals are then fed into the microcontroller MC9S12ZVLA as the PGA circuit inputs.
Following are the Register configurations done
PGAEN = 1;
PGAGAIN = 0x02; /* 40x*/
PGAOFFSET = 0x00; /*Disabled OFFSET*/
/* ==== Analog Mode Operation for HVI pin (IGN_FB). ==== */
PTAL_PTAENL = SET; /* 1 PL0 is connected to ADC */
PTAL_PTTEL = SET; /* Input buffer enabled when used with analog function */
PTAL_PTADIRL = CLEAR; /* Input voltage divider active on analog input to ADC channel */
PIRL_PIRL0 = 0x00; /* ratio selected 1:6 */
tPGA settling time given is 56us.
Vref of ADC is 5v.
When i sample first signal, its is getting Saturated to 0xFF (Higher than 2.6V) and other Saturated to 0x00 (Negative value less than 2.4V) .
Does anyone know if this could be a problem with the Mux or Settle timing tPGA? do you think we need more time?
I want to know How long does it take to sample the whole command sequence list to the ADC?
Thanks in advance