AnsweredAssumed Answered

About GPIO interruption in i.MX6SL.

Question asked by Keita Nagashima on Feb 16, 2016
Latest reply on Feb 29, 2016 by Christopher Telemann

Dear All,


Hello. I would like to know the relation of GPIOx_DR and GPIOx_IMR in i.MX6SL.

GPIOx_IMR was all cleared by GPIOx_DR register.



1. Set GPIO5_IMR = 0x000000c0     // To use the GPIO5[6] & GPIO5[7]

2. Set GPIO5_DR =0x0000f000     // Set the 12 to 15 bit

--> As a result, GPIO5_IMR = 0x00000000 (All cleared! masked.)



Why is GPIOx_IMR cleared by setting GPIOx_DR?




Best Regards,