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IMX6DQ6SDLHDG pdf

Question asked by J Burk on Feb 12, 2016
Latest reply on Feb 16, 2016 by Artur Petukhov

Regarding section 3.5.6 Four chips T topology routing examples: the pdf shows three layers of DDR3 routing, but there is clearly a fourth layer used that isn't shown. Would it be possible to get a screenshot of the missing layer?

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