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MPC5674F QADC DMA Data Swap Problem

Question asked by Umit Kayacik on Feb 11, 2016
Latest reply on Feb 15, 2016 by David Tosenovjan

Hi,

 

I have a problem with QADC and EDMA continuous conversion. My code is like below, Actually I used example "Example_MPC5674F-eQADC+eDMA-Continuous_Scan-v0_1-CW210.zip".

 

uint32_t CQueue_B_0[] =

{

    ( CHANNEL(0)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(1)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(2)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(3)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(4)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(5)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(6)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(7)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(8)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(9)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(10)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(11)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(12)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(13)  | B0 | MESSAGE_TAG(RFIFO0)         ),

    ( CHANNEL(14)  | B1 | MESSAGE_TAG(RFIFO0) | EOQ   )

};

 

I set up a QADCB init for continuous conversion like below, (I dont use interrupt)

 

void INITQADCB(void)

{

  #define SINGLE_SCAN_B_TRIGGER_Q0 EQADC_B.CFCR[0].R=0x0410

  #define SINGLE_SCAN_B_TRIGGER_Q1 EQADC_B.CFCR[1].R=0x0410

 

  #define FISR_EOQ_MASK 0x10000000

 

  #define ADC_configuration 0x8004

 

  EQADC_B.MCR.R = 0x00000000; //debug mode

 

  // write to indirectly mapped ADC configuration register

  // set prescaler and enable ADC0

  EQADC_B.CFPR[1].R = ADC_REG_ADDR(ADC0_CR)  | ADC_REG_VALUE(ADC_configuration)  | B0;

 

  // set prescaler and enable ADC1

  EQADC_B.CFPR[1].R = ADC_REG_ADDR(ADC1_CR) | ADC_REG_VALUE(ADC_configuration)  | B1  | EOQ;

 

  // Trigger CFIFO 1 using Single Scan SW mode

  SINGLE_SCAN_B_TRIGGER_Q1;

 

  // Wait for End Of Queue flag

  while (EQADC_B.FISR[1].B.EOQF !=1)

  {

  }

 

  // Clear End Of Queue flag

  EQADC_B.FISR[1].R = FISR_EOQ_MASK;

 

  EQADC_B.IDCR[0].R = //EQADC_A_IDCR_PIE0_MASK    | // Pause Interrupt Enable

  //EQADC_A_IDCR_EOQIE0_MASK  | // End of Queue Int. Enable

  EQADC_B_IDCR_CFFE0_MASK   | // CFIFO Fill Enable

  EQADC_B_IDCR_CFFS0_MASK   | // CFIFO Filled by DMA

  EQADC_B_IDCR_RFDE0_MASK   | // RFIFO Drain Enable

  EQADC_B_IDCR_RFDS0_MASK   ; // RFIFO Drained by DMA

 

 

  EQADC_B.CFCR[0].R = MODEx(SOFTWARE_TRIGGER_CONTINUOUS_SCAN);

}

 

DMA is like example but only I closed DMA ch after major loop is finished with

EDMA_B.TCD[CFIFO_0_DMA_chnl].D_REQ = 1;

 

and I have a trigger function, after all conversions finished :

 

void Trigger(void)

{

  /* Wait for End Of Queue flag */

  /* Be sure CFIFO DMA is finished the process */

  while (EQADC_B.FISR[0].B.EOQF != 1)

  {

  }

  /* Clear End Of Queue flag */

  EQADC_B.FISR[0].R = 0x10000000;

 

 

    /* Be sure RFIFO DMA is finished the process */

  while (EDMA_B.TCD[RFIFO_0_DMA_chnl].DONE == 0){}

 

  /*-- pop converted ch results to clean buf --*/

  for (i= 0; i< 15; i++)

  {

     ADCResults[i] = (RQueue_B_0[i] >> 2u ) & 0xFFFF;

  }

 

  /*-- Trigger ADC CFIFO registers to QADCA peripheral --*/

  EDMA_B.SERQR.R = CFIFO_0_DMA_chnl;

  EDMA_B.SERQR.R = RFIFO_0_DMA_chnl;

 

}

 

Problem is conversion results are shifted to other channels and I couldnt find any reasonable answer. I call this trigger func within ms interval and conversion is well at first times, after 3-16 minutes sometimes 3 sometimes, sometimes 11 minutes ADC channel results are shifted. Could you please help me to solve this problem ?

 

Arry 0 ------------ ch0-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 1 ------------ ch1-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 2 ------------ ch2-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 3 ------------ ch3-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 4 ------------ ch4-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 5 ------------ ch5-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 6 ------------ ch6-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 7 ------------ ch7-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 8 ------------ ch8-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 9 ------------ ch9-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 10 ------------ ch10-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 11 ------------ ch11-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 12 ------------ ch12-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 13 ------------ ch13-  CFIFO0 ---- ADC0 ---- RFIFO0

Arry 14 ------------ ch14-  CFIFO0 ---- ADC0 ---- RFIFO0

 

ch0 result goes to Arry 12 instead of Arry0. Other ch results are shifted with this rate.

 

Not: Is there any CFIFO SW Trigger need after "EDMA_B.SERQR.R = RFIFO_0_DMA_chnl;", if needs is there any example usage?

 

Best Regards,

Umit.

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