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SPI MQX receive buffer only even buffer correct mk60

Question asked by jparrish88 on Feb 10, 2016
Latest reply on Feb 16, 2016 by Henry Le

The initialization of SPI is the same in bootcode and firmware:


static void init_SPI_Channel(SPI_MemMapPtr spi_ptr, uchar ucFlagMaster)

uint_32 ctar;

   ctar= 0x7E000000; //frame size 16

//CPOL= 1 //CPHA= 1

//Big Endian


   /* Disable and clear SPI */

   spi_ptr->MCR &= (~SPI_MCR_MDIS_MASK);



   spi_ptr->CTAR[0] = ctar;


   /* Receive FIFO overflow enable */

   spi_ptr->MCR |= SPI_MCR_ROOE_MASK;


   /* Set CS0-7 inactive high */

   spi_ptr->MCR |= SPI_MCR_PCSIS(0xFF);


   /* Disable interrupts */

   spi_ptr->RSER = 0;


   /* Clear all flags */

   spi_ptr->SR = ~SPI_SR_TFFF_MASK;




   /* Enable SPI module */

   spi_ptr->MCR &= (~SPI_MCR_HALT_MASK);



The ISR to receive data on SPI is the same in bootcode and firmware:


__attribute__ ((interrupt("IRQ")))void ISR_SPI_SLAVE(void)


       SPI_MemMapPtr spi_ptr= (SPI_MemMapPtr)RH_SPI_SLAVE_PTR;



       while (spi_ptr->SR & SPI_SR_RFDF_MASK)


static uchar *ucRxPtr;

uint16_t uiData      = spi_ptr->POPR;

spi_ptr->SR = SPI_SR_RFDF_MASK;

if ( g_RHspi.uiSlaveTimeout == 0 )


  ucRxPtr       = (uint8_t*)&(g_RHspi.buf[g_RHspi.uiBufNum].ucRx_buf[0]);



*ucRxPtr++= ((uiData>>8)& 0x0ff);

*ucRxPtr++= (uiData & 0x0ff);

g_RHspi.uiSlaveTimeout= 2;

g_RHspi.uiSlaveRxCnt+= 2;






The code works correctly in Boot, but once it's inside MQX it develops an issue where the data received on even buffer indexes are the correctly received values, but the odd bytes are shifted in memory by 6 index slots. So if byte 9 is incorrect, the correct byte will be at byte 15 and byte 10 is the correct byte that should have been received.


Debug has only given me: "RESERVED_X” registers are all 0xBA in firmware, where they have various values in bootcode