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Relation between PLL Freq and SSI's sys clock

Question asked by Yehuda Stern on Feb 10, 2016
Latest reply on Feb 12, 2016 by Yehuda Stern

Hi,

 

1.  The relation between PLL Freq and SSI's sys clock is given by SSIDIV (in CCM).   Is that the product of SSIx_clk_pred and SSIx_clk_podf ?

     (I set PLL4 frequency to 688.128 MHz and SSIDIV to 56, and would expect SSI's sys clock to be 12.288 MHz).

 

2.  mxc_wm8962_init() function in board-mx6q_sabresd.c includes the following code:

     rate = clk_round_rate(clko, 24000000);

     clk_set_rate(clko, rate);

     wm8962_data.sysclk = rate;

 

     But when I read wm8962_data.sysclk, I receive 86.016 MHz, which is 7 times the expected value.

     What's the purpose of this code?  Can it simply be replaced with:   rate = clk_set_rate(clko, 12288000);  ?

 

3.  When measuring the Serial BIT clock with a scope, I always get 1.4112 MHz instead of 1.536 MHz.  

      Any idea why?  (is that the default value given by the driver?)

 

Thanks

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