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K70 DDR2 controller issue

Question asked by Luca Staiano on Feb 10, 2016
Latest reply on May 26, 2016 by Luca Staiano

Goodmorning community.

I have some problems using DDR2 controller on a kinetis K70 microcontroller. In details if i write and read 8 bit or 16 bit data, i can write a specific value in a location and read back the same value. If i do the same thing using 32bit data, i write a value but i read back a different value on same location.

Note that, if I add a delay after each write and read operation, in this case I can read back the correct value also for 32 bit data.

 

Controller initialization is the following:

 

  /* Enable DDR controller clock */

  SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;

 

  /* Enable DDR pads and set slew rate */

  SIM_MCR |= 0xC4;   /* bits were left out of the manual so there isn't a macro right now */

 

  /* Software Reset */

  DDR_RCR |= DDR_RCR_RST_MASK;

 

  /* 10 Buffers, 150 ohm on ODT PAD CS0 */

  DDR_PAD_CTRL = 0x01000203;

 

  /* Set DRAM Class DDR2 */

  DDR_CR00 = 0x00000400;

 

  /* DDR_CR01 default on power on  :

     CSMAX = 2

     MAXCOL CR25[COLSIZ] = 11b

     MAXROW CR25[ADDPINS]  10000b - Nr of rows */

 

 

  DDR_CR02 = 0x02000031;

 

  DDR_CR03 = 0x02020506;

 

  DDR_CR04 = 0x06090202;

 

  DDR_CR05 = 0x02020302;

   

  DDR_CR06 = 0x00904002;

 

  DDR_CR07 = 0x01000303;

 

  DDR_CR08 = 0x05030201;

 

  DDR_CR09 = 0x020000c8;

 

  DDR_CR10 = 0x03003207;

 

  DDR_CR11 = 0x01000000;

 

  DDR_CR12 = 0x04920031;

 

  DDR_CR13 = 0x00000005;

 

  DDR_CR14 = 0x00C80002;

 

  DDR_CR15 = 0x00000032;

 

  DDR_CR16 = 0x00000001;

 

  /* DDR_CR17 default value */

 

  /* DDR_CR18 default value */

 

  /* DDR_CR19 default value */

 

  DDR_CR20 = 0x00030300;

 

  DDR_CR21 = 0x00040232;

 

  DDR_CR22 = 0x00000000;

 

  DDR_CR23 = 0x00040302;

 

  /* DDR_CR24 default value */

 

  DDR_CR25 = 0x0A010201;

 

  DDR_CR26 = 0x0101FFFF;

 

  DDR_CR27 = 0x01010101;

 

  DDR_CR28 = 0x00000003;

 

  DDR_CR29 = 0x00000000;

 

  DDR_CR30 = 0x00000001;

 

  DDR_CR34 = 0x02020101;

 

  /* DDR_CR35 default value */

 

  DDR_CR36 = 0x01010201;

  

  DDR_CR37 = 0x00000200;

   

  DDR_CR38 = 0x00200000;

   

  DDR_CR39 = 0x01010020;

 

  DDR_CR40 = 0x00002000;

 

  DDR_CR41 = 0x01010020;

   

  DDR_CR42 = 0x00002000;

   

  DDR_CR43 = 0x01010020;

   

  DDR_CR44 = 0x00000000;

 

  DDR_CR45 = 0x03030303;

   

  DDR_CR46 = 0x02006401;

 

  DDR_CR47 = 0x01020202;

   

  DDR_CR48 = 0x01010064;

 

  DDR_CR49 = 0x00020101;

 

  DDR_CR50 = 0x00000064;

 

  /* DDR_CR51 default value */

 

  DDR_CR52 = 0x02000602;

   

  DDR_CR53 = 0x00000000;

   

  /* DDR_CR54 default value */

 

  /* DDR_CR55 default value */

 

  DDR_CR56 = 0x02030000;

 

  DDR_CR57 = 0x01000000;

 

  /* DDR_CR58 default value */

  /* DDR_CR59 default value */

  /* DDR_CR60 default value */

  /* DDR_CR61 default value */

  /* DDR_CR62 default value */

  /* DDR_CR63 default value */

 

  asm("NOP");

 

  DDR_CR00 |= 0x00000001;

 

  while ((DDR_CR30 & 0x400) != 0x400)

  {

 

  }

 

  MCM_CR |= MCM_CR_DDRSIZE( 1 );   

 

Do you have any ideas about this behaviour?

 

Many thanks,

 

Luca

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