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T1042 SerDes Options: SATA on LaneG

Question asked by Stefan Lange on Feb 8, 2016
Latest reply on Mar 29, 2016 by Stefan Lange

Hello NXP team,

 

we have designed a T1042 module with a starterkit and would like to test the SATA interface on SerDes Lane G.

TQMT1040RM Rev0 figure 31-1 on page 1723 shows the supported SerDes options.

 

Option 0x88 would be the relevant one for us in this case.

 

However upon setting the RCW SRDS_PRTCL_S1 bits to 0x88, UBoot prints:

Corenet Platform Cache: 256 KiB enabled

Using SERDES1 Protocol: 136 (0x88)

SERDES1[PRTCL] = 0x88 is not valid

..

 

Looking at the UBoot code in

arch/powerpc/cpu/mpc85xx/t1040_serdes.c

I noted that 0x88 is not an option in the serdes_cfg_tbl:

 

static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {

  [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE3, SATA2, SATA1},

  [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},

  [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

  PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},

  [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

  PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},

  [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

};

 

Is there a particular reason for this, have I overread something in the reference manual?

Please advise.

 

 

Thanks and best regards,

Stefan

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