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MC56F8023 I2C does not meet timing

Question asked by J Nguyen on Feb 5, 2016
Latest reply on Feb 11, 2016 by Stanislav Arendarik

Hello,

 

I tried to contact NXP support for this issue, but they are dreadfully slow at replying.  I hope you guys are better! 

 

We are having issues with the MC56F8023 doing I2C.  It looks like the SDA is falling at the same time as SCL, resulting in a negative hold time.  Section 10.12 of the spec says that the hold time (tHD; DAT) is at least 0.  If SDA and SCL fall at the same time, that is impossible to be 0 because Figure 10-14 shows that tHD; DAT is defined when SCL is at VIL and SDA is at VIH.  We have looked at the waveforms using an oscilloscope and it shows a negative hold time.  In addition, we've connected the pins to an I2C analyzer and it also affirms that the hold time is negative and it is incorrectly reading data because of this.

 

I tend to believe that we have something set wrong in CodeWarrior, as I find it hard to believe that NXP/Freescale would so obviously miss something like this and release this chip with a huge flaw.  Where can I set the hold time in CodeWarrior or what are we doing wrong?

 

Thanks!

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