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Wait for PLL lock with S912XEG128J2MMA

Question asked by KWANGHO PARK on Feb 5, 2016
Latest reply on Feb 11, 2016 by youngcheol song

I have an issue that this wait time is very long ( 1 sec ~ 10min.) to exit this wait loop sometimes at out production line

- we found this issue only one time that the product have this issue.   it is difficut to reproduce when this situation was found. almost could not reproduce,

- but,Some failure was found due to related this issue in the field, 

 

we have assembled 100 product with S912XEG128J2MMA recently.

There are 3 product that have this issue

- 1 product takes 15 second to exit this loop only 1 time, could not reproduce after that.

- 2 product takes 15 min  to exit this loop only 1 time, could not reproduce after that.

 

Could you advice me this issue?

 

 

the wait loop of the firmware is generated by Processor Expert of Codewarrior IDE, the loop is as follows

void _EntryPoint(void)
{
  /* ### MC9S12XEG128_80 "Cpu" init code ... */
   .................
  while(CRGFLG_LOCK == 0U) {           /* Wait until the PLL is within the desired tolerance of the target frequency */
  }
  /* CLKSEL: PLLSEL=1 */
  setReg8Bits(CLKSEL, 0x80U);          /* Select clock source from PLL */
  /* VREGHTCL: ??=0,??=0,VSEL=0,VAE=1,HTEN=0,HTDS=0,HTIE=0,HTIF=0 */
  setReg8(VREGHTCL, 0x10U);            
  /*** End of PE initialization code after reset ***/
  /*lint -save  -e950 Disable MISRA rule (1.1) checking. */
  __asm("jmp _Startup");               /* Jump to C startup code */
  /*lint -restore Enable MISRA rule (1.1) checking. */
}

#pragma CODE_SEG DEFAULT
/* END Cpu. */

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