AJay Jadhav

S12XS - interrupt controlled hardware finite state machine

Discussion created by AJay Jadhav on Feb 15, 2008
Latest reply on Feb 15, 2008 by kef

Hi,

I read following statement in some forum,

"current controllers and flash devices have an internal interrupt

controlled hardware finite state machine to control the timing of the erase /

write operations."

I am writing flash driver for S12XS controller, I did not find any reference in datasheet where above statement can be proven.

Any pointers for same?

Thanks.

Regards,

 Ajay

 

 

Outcomes