I'm developing with BSC9131 and interfacing an ANT interface with AD9361
The common logic voltage levels are 1.8V.
In the BSC9131 spec, the requirements for ANT_REF_CLK should be 3.3v logic levels according to Table 18 and 19 (RF Parallel Reference Clock DC Electrical Characteristics), since it is fed with OVDD (3.3v)
But on the pinout table the ANT_REF_CLK pin is referenced to X2VDD
Also, on benetel Rerefence board they use the AD9362 which operates at 1.8v voltage levels and the XVDD voltage is set to 1.8v
Can someone please approve that ANT_REF_CLK should be a 1.8v clock?