I would like to ask about power-on sequence of i.MX6SL.
Are there any restriction on the order of rising of VDD_HIGH_IN and NVCC_1V8?
My customer thinks as below.
VDD_HIGH_IN and NVCC_1V8 should rise during POR=L, and there is no matter whether the order of the rises is VDD_HIGH_IN, NVCC_1V8 or vice versa.
Is it true?