We are developing the custom board with MKL16Z64VLH4 device.
When we forced the reset_b signal lelvel High -> Low ( assert the external pin reset),
What kind of sequence does KL16 boot up by?
Is it same POR boot sequence ?
POR boot sequence is as follows.
(the source is Reference Manual KL16P80M48SF4RM )
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCGis enabled in its default clocking mode.
2. Required clocks are enabled (system clock, flash clock, and any bus clocks that do
not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Reset Control logic
continues to drive the RESET pin out low.
4. Early in reset sequencing, the NVM option byte is read and stored to the FOPT
register of the Flash Memory module (FTFA_FOPT).
5. When flash Initialization completes, the RESET pin is released. If RESET continues
to be asserted the system continues to be held in reset. Once the RESET pin is detected
high, the core clock is enabled and the system is released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0.