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IMX6UL layout

Question asked by kaveh mohamadabadi on Feb 3, 2016
Latest reply on Feb 4, 2016 by igorpadykov



It seems that in the Layout of IMX6UL 9x9 evk board, the group of the high-speed signals (Data B0, B1 and Addr) are not routed on the same layer which is not suggested by the hardware design guide. Is the possible to follow the evk board design and routing the bus group in the different layers since imx6ul run at lower frequencies compare to the imx6s or imx6q families?

And where we can find the init scrip file for LPDDR2 stress test?