Designing a SoloX based board and connecting FPGAs using the EIM bus.
EIM will be configured as a 16-bit, multiplexed bus.
Plan would be to run this interface as a synchronous bus that supports burst accesses.
Looking through the various documents, including the SoloX reference manual, it is not clear to me where to find timing diagrams describing the external signals for this bus configuration. Looking for both non-burst and burst mode timing diagrams and/or descriptions to use in designing the FPGA interface logic.
Also, to implement a synchronous interface on the EIM it appears to be required to use the BCLK in continuous clock mode. Is that correct?
If no, then what clock is used for the bus interface?
If yes, then it's not clear how a burst mode is supported.
Also, in this mode, is the LBA signal essentially an address latch enable signal for the multiplexed bus?