Data reception on Falling edge in UCC transparent mode

[amanagantivinod]

Hi All,

We are using P1021 rdb in our ISDN gateway design, we are developing V.35 protocol software by making use  of EXAR transceiver and UCC in transparent mode with NMSI configuration.

Is there any register setting available to make changes in the clock edge selection for reception and transmission in UCC transparent NMSI mode?

As per our requirement data must be received on the falling edge and send on the raising edge, how can we achieve this, if there is no specific register setting can we use transmit clock inversion option for achieving this?

What encoding will be used in general for V.35 interface data?

How synchronization register, UDSR works in P1021?

Receive bit stream will be compared bit by bit OR after receiving a complete byte it will be compared with UDSR register?  Could you please explain us.

CD is asynchronous signal, if data is sent after two clocks of CD assertion by other end device, how can we achieve receive data stream synchronization(without bit shift) in UCC NMSI mode?

[alexander_yakov]

In the NMSI mode the only transmit edge may be changed by using TCI bit - "Transmit Clock Invert".

Transparent protocol does not use any encoding.

Receive stream is compared bit-by-bit in case if UDSR pattern is used. Note - in this mode you can not use CD.

If you use CD for sync, and there are several extra clock pulses before valid data, that there will be a bit shift.

Have a great day,
Alexander

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[amanagantivinod]

Hi Alexander,

Thanks for your in-detail clarification,

It really helped us, thanks once again (bow)

On Mon, Feb 1, 2016 at 8:17 PM, alexander.yakovlev <