KL27Z: DMA doesn't increment

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

KL27Z: DMA doesn't increment

398 Views
aihans
Contributor II

Hi,

I encountered a strange behaviour of the DMA and wanted to ask if I'm missing some point to get it working correctly.

I'm working on the FRDM-KL27Z board.

The idea is to measure from 2 ADC Inputs and save the data inside a buffer.

I'm trying an approach like described in AN4590, just without the PDB trigger.

The raw funcionality should be to trigger the ADC in software mode and safe the result inside a buffer.

In Detail:

- ADC reads Input 1 and writes inside ADC0_RA

- COCO is set and DMA0 is set to start at  peripheral request from ADC

- DMA0 Transfers data to a buffer and increments

- DMA1 is linked to start after DMA0 finishes

- DMA1 reads a value from an array and writes it to ADC0_SC1A, then increments the sopurce array

- ADC now starts a new conversion on the channel described inside the Array

And from here everything starts over.

After completing a whole cyclus an interrupt is called, which resets the destination address of DMA0 and the source address of DMA1.

Everything works, except one little detail:

DMA0 does not increment if DMA1 triggers a new ADC conversion.

The channel is changed and the result written inside the correct destination buffer, but always inside the first address of this buffer.

Has anyone ever encountered such a behaviour?

I'll post the DMA and ADC settings at the end of this post.

Best regards,

Hans

ADC:

ADC0_CFG1_Mode = 11

ADC0_SC2_DMAEN = 1

DMA0:

DMA_DCR0_EINT = 1

DMA_DCR0_ERQ = 1

DMA_DCR0_CS = 1

DMA_DCR0_EADREQ = 1

DMA_DCR0_SSIZE = 10

DMA_DCR0_DSIZE = 10

DMA_DCR0_DINC = 1

DMA_DCR0_DREQ = 1

DMA_DCR0_LINKCC = 10

DMA_DCR0_LCH1 = 01

DMAMUX0_CHCFG0_SOURCE = 0d40 (ADC0)

DMA1:

DMA_DCR1_EINT = 1

DMA_DCR1_ERQ = 1

DMA_DCR1_CS = 1

DMA_DCR1_EADREQ = 1

DMA_DCR1_SSIZE = 01

DMA_DCR1_DSIZE = 01

DMA_DCR1_SINC = 1

DMA_DCR1_DREQ = 1

DMAMUX0_CHCFG1_SOURCE = 0d60 (always on)

0 Kudos
1 Reply

270 Views
jeremyzhou
NXP Employee
NXP Employee

Hi,

After I've had a brief look through the code, I found that you already set the DMA_DCR0[DINC]=1 which enable the DAR increments by 1,2,4 depending upon the size of the transfer.

So I also feel weird, and I'd highly recommend you to refer to the thread for details.

PIT- ADC- DMA Example for FRDM-KL25z, FRDM-K64F, TWR-K60D100 and TWR-K70

Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos