我需要使用MCIMX6Q6AVT10AC 的EIM接口读取FPGA,
我把imx6q的EIM_DA0----EIM_DA13作为RAM地址线,EIM_D16---EIM_D31作为RAM的数据线。使用了EIM_RW EIM_OE EIM_CS0
EIM_WAIT EIM_EB0 EIM_EB1,与FPGA相连
我按照board-mx6q_sabreauto.h和board-mx6q_sabreauto.c中的weimnor例子做了如下改动:
====================================================================================
1,
我在linux内核,在board-mx6q_sabresd.h中增加了
static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = {
/* Parallel NOR */
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,
MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,
MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1,
/*Control NOR reset using gpio mode*/
//MX6Q_PAD_DISP0_DAT8__GPIO_4_29,
MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,
MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,
/* Parallel Nor Data Bus */
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,
MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,
MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,
MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,
MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24,
MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25,
MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26,
MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27,
MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28,
MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29,
MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30,
MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31,
/* Parallel Nor 25 bit Address Bus */
MX6Q_PAD_EIM_A24__GPIO_5_4,
MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,
MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,
MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,
MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,
MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,
MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,
MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,
MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,
MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
};
====================================================================================
2,在board-mx6q_sabresd.c中增加了
static struct mtd_partition mxc_nor_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = SZ_256K,
}, {
.name = "bootenv",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
}, {
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct resource nor_flash_resource = {
.start = CS0_BASE_ADDR,
.end = CS0_BASE_ADDR + 0x02000000 - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data nor_flash_data = {
.probe_type = "map_rom",
.width = 2,
.parts = mxc_nor_partitions,
.nr_parts = ARRAY_SIZE(mxc_nor_partitions),
};
static struct platform_device physmap_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &nor_flash_data,
},
.resource = &nor_flash_resource,
.num_resources = 1,
};
/* These registers settings are just valid for Numonyx M29W256GL7AN6E. */
static void mx6q_setup_weimcs(void)
{
void __iomem *nor_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);
void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);
unsigned int reg;
struct clk *clk;
u32 rate;
/* CLKCTL_CCGR6: Set emi_slow_clock to be on in all modes */
reg = readl(ccm_reg + 0x80);
reg |= 0x00000C00;
writel(reg, ccm_reg + 0x80);
/* Timing settings below based upon datasheet for M29W256GL7AN6E
These setting assume that the EIM_SLOW_CLOCK is set to 132 MHz */
clk = clk_get(NULL, "emi_slow_clk");
if (IS_ERR(clk))
printk(KERN_ERR "emi_slow_clk not found\n");
rate = clk_get_rate(clk);
if (rate != 132000000)
printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"
" WEIM NOR timing may be incorrect!\n");
/*
* For EIM General Configuration registers.
*
* CS0GCR1:
* GBC = 0; CSREC = 6; DSZ = 2; BL = 0;
* CREP = 1; CSEN = 1;
*
* EIM Operation Mode: MUM = SRD = SWR = 0.
* (Async write/Async page read, none multiplexed)
*
* CS0GCR2:
* ADH = 1
*/
writel(0x00626481, nor_reg);//writel(0x00620081, nor_reg);
writel(0x00000001, nor_reg + 0x00000004);
/*
* For EIM Read Configuration registers.
*
* CS0RCR1:
* RWSC = 1C;
* RADVA = 0; RADVN = 2;
* OEA = 2; OEN = 0;
* RCSA = 0; RCSN = 0
*
* CS0RCR2:
* APR = 1 (Async Page Read);
* PAT = 4 (6 EIM clock sycles)
*/
//writel(0x1C022000, nor_reg + 0x00000008);
//writel(0x0000C000, nor_reg + 0x0000000C);
writel(0x0b010000, nor_reg + 0x00000008);
writel(0x00000008, nor_reg + 0x0000000C);
/*
* For EIM Write Configuration registers.
*
* CS0WCR1:
* WWSC = 20;
* WADVA = 0; WADVN = 1;
* WBEA = 1; WBEN = 2;
* WEA = 1; WEN = 6;
* WCSA = 1; WCSN = 2;
*
* CS0WCR2:
* WBCDD = 0
*/
//writel(0x1404a38e, nor_reg + 0x00000010);
writel(0x0b040040, nor_reg + 0x00000010);
writel(0x00000000, nor_reg + 0x00000014);
}
====================================================================================
3,在board-mx6q_sabresd.c中的函数mx6_sabresd_board_init(void)增加了
mx6q_setup_weimcs();
platform_device_register(&physmap_flash_device);
======================================================================================
现在我想通过IMX6Q的EIM接口访问RAM(fpga),以上的设置是否正确,还有EIM_CS0GCR1:
EIM_CS0GCR2: EIM_CS0RCR1:EIM_CS0RCR2: EIM_CS0WCR1: EIM_CS0WCR2的值应该是多少。
那么在我的应用程序当中,我应该用那种方式读写FPGA中的RAM。
你好
我现在也在使用emi和fpga进行总线通信,读取fpga内部的数据,但是我现在遇到了一些问题,通过dma进行数据传输的时候,总线上没有任何信号发生,不知道你是否把这个通信测试成功,如果成功的话,非常希望你能给予我一定的帮助,非常感谢
郭瑞
Hello rui guo
I'm doing the same working now , it seems that u have realised the function connecting EIM to FPGA, can u give me some help?
Hi Shan
please try eim settings as in attached sdk example.
Best regards
igor
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