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OSBDM versus TBDML BDM hardware interface

Question asked by pgo on Feb 14, 2008
Latest reply on Jun 25, 2008 by Dan Leech
I have a number of TBDML boards that use 74LCV2G125 as the BDM interface IC.  This is a quad 3-state buffer.  I've been able to adapt the OSBDM code to work with these quite easily but in the process I have a question about the operation of the OSBDM boards that use the 74LVC1T45 ICs (a single bi-directional buffer). 
In the TBDML boards the BDM_IN(PTA.6) and BDM_OUT(PTA.7) pins are isolated while in the OSBDML they are connected together to form BDM_INOUT.  My query relates to how this works in the bdm_rx() routines.  These routines need to be able to drive the BDM pin Low and then 3-state(to read the BDM input value).  It does this by manipulating BDM_INOUT via PTA.7,  and controlling the direction of the 74LVC1T45 buffer using  BDM_DIR(PTA.4).  The relevent code is as follows:
1.   CLRX                    // prepare HX to point to PTA
2.   CLRH
3.   LDA   #RESET_OUT_MASK  // contents of A will be driven to PTA in order to switch the driver off
3a. STA    ,X    /* PTA.7=0, PTA.4=0  (1T45 is BDM_INOUT <= BDM pin)    BDM high impedance */
/* Read a single bit */
4.   BSET  7,0  /* PTA.7=1 , PTA.4=0  (1T45 is BDM_INOUT <= BDM pin)    BDM high impedance */
5.   COM   ,X    /* PTA.7=0, PTA.4=1  (1T45 is BDM_INOUT => BDM pin)    drive BDM low */
6.   STA    ,X    /* PTA.7=0, PTA.4=0  (1T45 is BDM_INOUT <= BDM pin)    BDM high impedance */
7.   LDX    ,X    /* PTA.7=0, PTA.4=0  (1T45 is BDM_INOUT <= BDM pin) load X with BDM_IN */
8.   PSHX        /* store the value on the stack */
9.   CLRX        /* clear X again */

The bit I don't understand is that (for speed reasons?) the code doesn't change the direction of PTA.7 anywhere so I would expect there to be a bus conflict in lines 6,7,8 etc. between PTA.7 and the '1T45.

The above code (with some polarity changes) would work fine with the 74LCV2G125.

Can anyone explain this?  Have I missed something?

Thanks


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