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IPU DI clock of i.mx6

Question asked by Zongbiao Liao on Jan 26, 2016
Latest reply on Jan 27, 2016 by Artur Petukhov

Hello, Community


I have two questions about IPU DI clock of i.mx6.



In page 2943 of IMX6SDLRM(Rev.2 04/2015), there is description as bellow.



DOWN - This parameter defines the offset from the beginning of the "RUN section"

to the negation of the signal; it is defined by the di#_cnt_down_<N> field, where N

is the counter's index. In case where DOWN < UP the waveform will have a 50%

duty cycle.



In the bold part above,what does the waveform refer to? Is it refer to the waveform of display's

interface clock?

But according to my test,I found that the duty cycle of the waveform of display's interface clock is

just related to IPU_DI#_BS_CLKGEN0 and IPU_DI#_BS_CLKGEN1. If di#_disp_clk_up is set

to 0, and di#_disp_clk_down is set to the half of di#_disp_clk_period, then the clock's waveform

will have a 50% duty cycle.


Is my opinion right?



According to my test and the BSP source code(L3.14.28), I found that the

componnent_size_i field and di0_access_size_i field of IPU_DI#_DW_GEN_i must be smaller than

di#_disp_clk_period field of IPU_DI#_BS_CLKGEN0.

Why cannot di0_access_size_i be equal to di#_disp_clk_period? Please tell me the reason.


Best Regards.