We are developing an IMX6 Solo/Quad common design and have seen a reference that states that applying a 32.768kHz external clock to RTC_XTAL1 can reduce boot time. I cannot find an ap-note that describes this or addresses possible concerns. Reading this forum and t6eh datasheetss, we see that the main considerations are that VDD_SNVS is powered, POR_B remains asserted until the clock is stable, XTAL0 left floating with a clock in to RTC_XTAL1, and that the peak amplitude of the clock must not exceed VDD_SNVS.
We would like to ask a few questions.
1 - does the use of an external 32kHz clock improve boot time?
2 - are the assumptions above correct?
3 - does the input to RTC_XTAL1 need to be AC coupled and is a series resistor required?
4 - are there other aspects to implementing an external 32k clock that NXP recommends or an AP note or reference design I should have referenced?
Thanks for your consideration,