I am triggering ADC0 via PDB. On conversion complete the ADC "triggers" the DMA channel, to write the conversion result to a RAM buffer. Since i have 3 inputs to the ADC and need 1024 samples per channel, i use the DMA scatter/gather feature to overload the TCD of the DMA channel with channel linking to perform another minor loop to update the ADCs SC1x register with the next input channel.
So far it seems to be working, but the order of entries in the SRAM buffer is not what I was hoping for. The first 510 entries are shifted into a new order (3-1-2), the next 510 entries order 2-3-1, the next 1-2-3 and so on..
I have attached my implementation, and would like to ask what I am doing wrong here, since I would love every entry in the order 1-2-3 as defined in the source array.
Thank you for your inputs,
Original Attachment has been moved to: _dma.c.zip