I want read a NOR flash using FCM of p4080 board. I am successful in reading its manufacture ID but when i want to read a page of the flash, it shows error in elbc's error register.Has anyone read a page of NOR flash ? I am using code warrior 10.1.
Sorry, the request is not clear.
The FCM controls NAND Flash devices - not NOR.
It could be useful to update the CodeWarrior because current version is 10.5.
Please explain the sequence you've performed in the CodeWarrior and provide corresponding screenshots.
Yes, it is NAND flash. I mistook.
Following i have done-
I have NAND08Gw3B2C- 8 Gbits (1 GB)- block size 128K + 4K bytes with page size 2112
Wrote a perogram to read page 5 of block1
1. The base address of NAND FLASH IS 0xFFA00000
so BR1 = 0xffa00821 - Data error checking disabled No ECC generation for FCM.
2. OR1 = 0xc0000796 -(AM is 1100_0000_0000_0000_0 for 1 GB)
3. FCR=0x00300000 as commands 00, 30 for page read
4. To read block 1, FBAR=0x00000001.
5. To read page5, FPAR=0x00005000
6. For reading entire page of block 1, FBCR =0x00000000
7. to Send commands from FCR and wait for BUSY/READY before reading in to buffer FIR=0x4125e000.
6. ECC disabled, 3 PageAddrs and 2 Column Addrs, FMR=0x0000f013
7. To special operation on bank 1, LSOR=0x00000001.
Then checked the buffer at (IMMR_BAse + elbc base addrs + 0x1000) for buffer 1.
But as seen in the snapshot, the said address in the above shows '???' and the LTEATR register shows error.
Attached are the snapshots.
I have successfully read the 'status reg' and 'identification/manufacture ID' but reading a page i am not successful at.
I believe that the U-Boot source code could be a good reference - please refer to the following link:
what does' oob ' stand for and can u send the link of .h files which are included in this code.
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Date:Thu, 28 Jan, 2016 at 9:17 am
Subject:Re: - NOR flash of P4080 using elbc's FCM machine
NOR flash of P4080 using elbc's FCM machine
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OOB means "Out-Of-Band" and corresponds to a dedicated NAND block area containing supplementary data including ECC:
Data Storage on NAND Flash | STLinux
Please install the PPCE500MC Linux SDK 1.9 to obtain complete U-Boot sources:
OR1[AM] should not be 1 GiB, especially not with a base address that is not 1 GiB-aligned. The eLBC SRAM is mapped into an 8 KiB address space, so the minimum address mask of 32 KiB will suffice.
You are also using the wrong address for the buffer. It is not in CCSR. It is at the address specified in BR1 (plus 0x1000 for page 1).
Retrieving data ...