imx6 duallite not able to reset the MT29PZZZ8D5BKFTF-18 W.95 single channel lpddr(1GB) 2 die

[swapniltiwari]

Hi

i have developed a new board using imx6dual and using single channel 2 die micron chipMT29PZZZ8D5BKFTF-18 W.95 and

using trace32 to intialize the lpddr2 using the script provided by the freescale.But i am not able to reset the lpddr2.

what are the steps through which i can assure whether i am able to communicate with lpddr2 itself . Can you provide me

the command through which i can read the device id etc from the lpddr2 so to ensure that my communication is happening

or not.

regards

swapnil

[igorpadykov]

Hi swapnil

i.MX6DL lpddr2 configuration is given in

i.MX6DL LPDDR2 Support for L3.0.35_4.0.0

pay attention that MMDC_MDISC[LPDDR2_2CH] = 0

and make sure that the DDR-SEL field for

IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET is set to '00'.

Communication with lpddr2 one can test using MRW,MRR

commands, check description of MMDCx_MDSCR in RM and example in

attached script MX6SL_EVK_LPDDR2_512MB_32bit_v0.9.inc.zip:

//=============================================================================
// LPDDR2 Mode Register Writes

//=============================================================================

setmem /32    0x021b001c =0x82018030    // MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=see Register Configuration

this command writes (MRW) 0x82 data to Mode 1 register (MMDCx_MDSCR bits 6-4 =0x3, 0x3 - Load Mode Register Command),

for MRR change thses bits to 0x6.

Best regards

igor

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[swapniltiwari]

Hi igor,

i tried reading lpddr2

setmem /32    0x021b001c =0x00008060 ;device info

setmem /32    0x021b001c =0x00508060;device id

setmem /32    0x021b001c =0x00608060;revision id1

setmem /32    0x021b001c =0x00708060;ervision id2

all result in MDMRR =0xFFFFFFFF

seems all are junk values. Can you suggest what could be the reason . I tried this after reset MRW command and with

other permutation nothing works.

regards

swapnil

[igorpadykov]

The data in this register is valid only when MDSCR[MRR_READ_DATA_VALID] is set to "1".

So you can have hardware issues, suggest to check lpddr2 signals with oscilloscope

~igor

[swapniltiwari]

Hi igor,

yes i am seeing MDSCR[MRR_READ_DATA_VALID] is set to "1" then also i am getting

all data FFFFFFFF

regards

swapnil

[igorpadykov]

Hi swapnil

suggest to check lpddr2 signals with oscilloscope

and verify what real data are provided by lpddr2

Best regards

igor

[swapniltiwari]

Hi igor,

we have already checked all the pins using oscilloscope its working fine  seems some issue in the lpddr2 setting only

can you cross verify the configuration that we are using in above reply.

regards

swapnil

[swapniltiwari]

Hi igor,

i have a sabre auto board with ddr3 can you pls let me know how to read device id,vendor id and

other information. 

regards

swapnil

[swapniltiwari]

Hi Igor,

here is the lpddr2 setting that i am using. pls let me know if my seetings are proper

//=============================================================================
//init script for i.Mx6DL LPDDR2
//=============================================================================
// Revision History
// v01
//=============================================================================
wait = on
//=============================================================================
// Disable	WDOG
//=============================================================================
setmem /16	0x020bc000 =	0x30
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
setmem /32	0x020c4068 =	0xffffffff
setmem /32	0x020c406c =	0xffffffff
setmem /32	0x020c4070 =	0xffffffff
setmem /32	0x020c4074 =	0xffffffff
setmem /32	0x020c4078 =	0xffffffff
setmem /32	0x020c407c =	0xffffffff
setmem /32	0x020c4080 =	0xffffffff
setmem /32	0x020c4084 =	0xffffffff
setmem /32	0x020c4018 =	0x00060324	//DDR clk to 400MHz
// Switch PL301_FAST2 to DDR Dual-channel mapping
//setmem /32	0x00B00000 =	0x1
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
setmem /32	0x020e0774 =	0x00080000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
setmem /32	0x020e0754 =	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
setmem /32	0x020e04ac =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
setmem /32	0x020e04b0 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
setmem /32	0x020e0464 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
setmem /32	0x020e0490 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
setmem /32	0x020e074c =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
setmem /32	0x020e0494 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
setmem /32	0x020e04a0 =	0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
setmem /32	0x020e04b4 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
setmem /32	0x020e04b8 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
setmem /32	0x020e076c =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
setmem /32	0x020e0750 =	0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
setmem /32	0x020e04bc =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
setmem /32	0x020e04c0 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
setmem /32	0x020e04c4 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
setmem /32	0x020e04c8 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
//setmem /32	0x020e04cc =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
//setmem /32	0x020e04d0 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
//setmem /32	0x020e04d4 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
//setmem /32	0x020e04d8 =	0x00003030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
setmem /32	0x020e0760 =	0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
setmem /32	0x020e0764 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS
setmem /32	0x020e0770 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS
setmem /32	0x020e0778 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS
setmem /32	0x020e077c =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS
//setmem /32	0x020e0780 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS
//setmem /32	0x020e0784 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS
//setmem /32	0x020e078c =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS
//setmem /32	0x020e0748 =	0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS
setmem /32	0x020e0470 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /32	0x020e0474 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /32	0x020e0478 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /32	0x020e047c =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
//setmem /32	0x020e0480 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
//setmem /32	0x020e0484 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
//setmem /32	0x020e0488 =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
//setmem /32	0x020e048c =	0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer:	Micron
// Device Part Number:	MT42L128M32D1TK-25
// Clock Freq.:	400MHz
// MMDC channels:	MMDC0
// Density per CS in Gb:	4
// Chip Selects used:	2
// Number of Banks:	8
// Row address:	14
// Column address:	10
// Data bus width	32
//=============================================================================
setmem /32	0x021b001c =	0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//setmem /32	0x021b401c =	0x00008000	// MMDC1_MDSCR, set the Configuration request bit during MMDC set up
setmem /32	0x021b085c =	0x1B4700C7	//MMDC0_MPZQLP2CTL,LPDDR2 ZQ params
//setmem /32	0x021b485c =	0x1B4700C7	//MMDC1_MPZQLP2CTL,LPDDR2 ZQ params
//=============================================================================
// Calibration setup.
//=============================================================================
setmem /32	0x021b0800 =	0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
//ca bus abs delay
setmem /32	0x021b0890  =	0x00400000	// values of 20,40,50,60,7f tried. no difference seen
//setmem /32	0x021b4890 =	0x00400000	// values of 20,40,50,60,7f tried. no difference seen
//Read calibration
setmem /32	0x021b0848 =	0x40404040	// MPRDDLCTL PHY0
//setmem /32	0x021b4848 =	0x40404040	// MPRDDLCTL PHY1
//Write calibration
setmem /32	0x021b0850 =	0x40404040	// MPWRDLCTL PHY0
//setmem /32	0x021b4850 =	0x40404040	// MPWRDLCTL PHY1
//dqs gating dis
setmem /32	0x021b083c =	0x20000000
setmem /32	0x021b0840 =	0x00000000
//setmem /32	0x021b483c =	0x20000000
//setmem /32	0x021b4840 =	0x00000000
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /32	0x021b081c =	0x33333333	// DDR_PHY_P0_MPREDQBY0DL3
setmem /32	0x021b0820 =	0x33333333	// DDR_PHY_P0_MPREDQBY1DL3
setmem /32	0x021b0824 =	0x33333333	// DDR_PHY_P0_MPREDQBY2DL3
setmem /32	0x021b0828 =	0x33333333	// DDR_PHY_P0_MPREDQBY3DL3
//setmem /32	0x021b481c =	0x33333333	// DDR_PHY_P1_MPREDQBY0DL3
//setmem /32	0x021b4820 =	0x33333333	// DDR_PHY_P1_MPREDQBY1DL3
//setmem /32	0x021b4824 =	0x33333333	// DDR_PHY_P1_MPREDQBY2DL3
//setmem /32	0x021b4828 =	0x33333333	// DDR_PHY_P1_MPREDQBY3DL3
//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /32	0x021b082c =	0xF3333333	// DDR_PHY_P0_MPREDQBY0DL3
setmem /32	0x021b0830 =	0xF3333333	// DDR_PHY_P0_MPREDQBY1DL3
setmem /32	0x021b0834 =	0xF3333333	// DDR_PHY_P0_MPREDQBY2DL3
setmem /32	0x021b0838 =	0xF3333333	// DDR_PHY_P0_MPREDQBY3DL3
//setmem /32	0x021b482c =	0xF3333333	// DDR_PHY_P1_MPREDQBY0DL3
//setmem /32	0x021b4830 =	0xF3333333	// DDR_PHY_P1_MPREDQBY1DL3
//setmem /32	0x021b4834 =	0xF3333333	// DDR_PHY_P1_MPREDQBY2DL3
//setmem /32	0x021b4838 =	0xF3333333	// DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//setmem /32	0x021b08c0 =	0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//setmem /32	0x021b48c0 =	0x24911492
// Complete calibration by forced measurement:
setmem /32	0x021b08b8 =	0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
//setmem /32	0x021b48b8 =	0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
// Channel0 - startng address 0x80000000
setmem /32	0x021b0004 =	0x00020036	// MMDC0_MDPDC
setmem /32	0x021b0008 =	0x00000000	// MMDC0_MDOTC
setmem /32	0x021b000c =	0x33374133	// MMDC0_MDCFG0
setmem /32	0x021b0010 =	0x00100A82	// MMDC0_MDCFG1
setmem /32	0x021b0014 =	0x00000093	// MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
setmem /32	0x021b0018 =	0x00001748	// MMDC0_MDMISC
setmem /32	0x021b001c =	0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
setmem /32	0x021b002c =	0x0F9F26D2	// MMDC0_MDRWD
setmem /32	0x021b0030 =	0x00000010	// MMDC0_MDOR
setmem /32	0x021b0038 =	0x00190778	// MMDC0_MDCFG3LP
setmem /32	0x021b0040 =	0x00000017	// Chan0 CS0_END
setmem /32	0x021b0400 =	0x11420000	// MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
setmem /32	0x021b0000 =	0xC3110000	// MMDC0_MDCTL
// Channel1 - starting address 0x10000000
//setmem /32	0x021b4004 =	0x00020036	// MMDC1_MDPDC
//setmem /32	0x021b4008 =	0x00000000	// MMDC1_MDOTC
//setmem /32	0x021b400c =	0x33374133	// MMDC1_MDCFG0
//setmem /32	0x021b4010 =	0x00100A82	// MMDC1_MDCFG1
//setmem /32	0x021b4014 =	0x00000093	// MMDC1_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
//setmem /32	0x021b4018 =	0x00001748	// MMDC1_MDMISC
//setmem /32	0x021b401c =	0x00008000	// MMDC1_MDSCR, set the Configuration request bit during MMDC set up
//setmem /32	0x021b402c =	0x0F9F26D2	// MMDC1_MDRWD
//setmem /32	0x021b4030 =	0x00000010	// MMDC1_MDOR
//setmem /32	0x021b4038 =	0x00190778	// MMDC1_MDCFG3LP
//setmem /32	0x021b4040 =	0x00000017	// Chan1 CS0_END
//setmem /32	0x021b4400 =	0x11420000	// MMDC1_MAARCR ADOPT optimized priorities. Dyn jump disabled
//setmem /32	0x021b4000 =	0xC3110000	// MMDC1_MDCTL
// Channel0 : Configure DDR device:
//CS0
setmem /32	0x021b001c =	0x003F8030	// MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
setmem /32	0x021b001c =	0xFF0A8030	// MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
setmem /32	0x021b001c =	0x82018030	// MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2
setmem /32	0x021b001c =	0x04028030	// MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
setmem /32	0x021b001c =	0x02038030	// MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6
//CS1
setmem /32	0x021b001c =	0x003F8038	// MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
setmem /32	0x021b001c =	0xFF0A8038	// MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
setmem /32	0x021b001c =	0x82018038	// MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2
setmem /32	0x021b001c =	0x04028038	// MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
setmem /32	0x021b001c =	0x02038038	// MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6
// Channel1 : Configure DDR device:
//CS0
//setmem /32	0x021b401c =	0x003F8030	// MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
//setmem /32	0x021b401c =	0xFF0A8030	// MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
//setmem /32	0x021b401c =	0x82018030	// MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2
//setmem /32	0x021b401c =	0x04028030	// MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
//setmem /32	0x021b401c =	0x02038030	// MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6
//CS1
//setmem /32	0x021b401c =	0x003F8038	// MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
//setmem /32	0x021b401c =	0xFF0A8038	// MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
//setmem /32	0x021b401c =	0x82018038	// MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2
//setmem /32	0x021b401c =	0x04028038	// MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
//setmem /32	0x021b401c =	0x02038038	// MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6
setmem /32	0x021b0800 =	0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
setmem /32	0x021b0020 =	0x00001800	// MMDC0_MDREF
//setmem /32	0x021b4020 =	0x00001800	// MMDC1_MDREF
setmem /32	0x021b0818 =	0x00000000	// DDR_PHY_P0_MPODTCTRL
//setmem /32	0x021b4818 =	0x00000000	// DDR_PHY_P1_MPODTCTRL
setmem /32	0x021b0004 =	0x00025576	// MMDC0_MDPDC now SDCTL power down enabled
//setmem /32	0x021b4004 =	0x00025576	// MMDC0_MDPDC now SDCTL power down enabled
setmem /32	0x021b0404 =	0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
//setmem /32	0x021b4404 =	0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
setmem /32	0x021b001c =	0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
//setmem /32	0x021b401c =	0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)