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i.mx6 solo on custom board : adv7182 video capture problem

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i.mx6 solo on custom board : adv7182 video capture problem

‎01-22-2016 03:13 AM
1,760 Views
michael_th
Contributor I

Hello,

I'm trying to capture a video stream coming from an adv7182 video decoder. The kernel version I’m using is the 3.0.35 from the bsp 4.0.0.

I know this is an old version but the project I’m working on is a derivative of an old project and porting everything would take too much time.

The video output pins are connected to csi0 :

pastedImage_1.png

The pads are muxed in this way :

/* i2c */

MX6DL_PAD_EIM_D21__I2C1_SCL,
MX6DL_PAD_EIM_D28__I2C1_SDA,    

/* video int */

MX6DL_PAD_EIM_D18__GPIO_3_18,

/* video reset */

MX6DL_PAD_EIM_D19__GPIO_3_19,

/* video power down */

MX6DL_PAD_EIM_D20__GPIO_3_20,

/* CSIO input */
MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_D_11,
MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19

As for the i2c, I modified the adv7180tv_in driver with the help of the register settings recommendations (https://ez.analog.com/servlet/JiveServlet/download/2633-26-29881/ADV7182%20RSD_revC.pdf ).
I also had to modify the gpr registers in the adv7180_io_init function : mxc_iomux_set_gpr_register(13, 0, 3, 4); Without that, i was getting " ERROR: v4l2 capture: mxc_v4l_read timeout counter 0" errors when i was trying to read from /dev/video0 like other people around here.

The /dev/video0 device file is successfully being created.  I’m trying to use gstreamer0.10 to record from the device :

gst-launch --verbose --eos-on-shutdown v4l2src ! ffmpegcolorspace ! jpegenc ! avimux ! filesink location=video.mov

[  430.855180] In MVC: mxc_v4l_do_ioctl c0485619
[  430.855185]    case VIDIOC_ENUMSTD
[  430.855194] In MVC:mxc_v4l_ioctl
[  430.855200] In MVC: mxc_v4l_do_ioctl c0485619
[  430.855205]    case VIDIOC_ENUMSTD
[  430.855213] In MVC:mxc_v4l_ioctl

This makes the mxc_v4l2_capture driver go in an infinite loop and the video file created has size 0.

What I also tried is to simply cat /dev/video0 :

root@BUI270:/home/appdata# cat /dev/video0

[   57.357205] Powering on adv7182

[   57.386266] imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_10 = 0x00000001

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[   58.026269] imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_10 = 0x00000001

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When I do that, I have some data burst every second, between each IPU warning message. I set the chip in freerun mode to display some color bar pattern. I could almost guess that this could represent some color bars if I could convert the data somehow.

I tried to compile gst-fsl-plugins to try the freescale v4l2src, but my Yocto project is not compatible. I had the same problem with gst-fsl-plugin_3.0.9.

I installed v4l-utils and tried some of the tools. v4l2grab gives an error :

root@BUI270:/home/appdata# v4l2grab -n 1

[ 1664.787257] Powering on adv7182

error 22, Invalid argument

and the mxc_v4l2_capture gives this debug code :

..

[ 1664.789476] In MVC: mxc_v4l_do_ioctl c050561a

[ 1664.789491]    case VIDIOC_ENUMINPUT

[ 1664.790569] In MVC:mxc_v4l_ioctl

[ 1664.790593] In MVC: mxc_v4l_do_ioctl c0445624

[ 1664.790610]    case default or not supported

[ 1664.790694] In MVC:mxc_v4l_ioctl

[ 1664.790718] In MVC: mxc_v4l_do_ioctl c0cc5640

[ 1664.790734]    case default or not supported

[ 1664.792678] In MVC:mxc_v4l_close

[ 1664.792708] adv7180 0-0020: adv7180:ioctl_s_power

[ 1664.793682] mxc_v4l_close: release resource

[ 1664.793705] MVC: In mxc_free_frame_buf

[ 1664.793722] In MVC:mxc_free_frames

Has somebody been facing similar issues with this video decoder ? Thank you in advance for your help !

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4 Replies

‎01-26-2016 06:16 AM
868 Views
CarlosCasillas
NXP Employee
NXP Employee

Hi Michael,

We are internally reviewing your case. In the meantime, could you please help us mentioning who is the FAE that is helping with this case?

We will be waiting for your reply.

Best regards!

/Carlos

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‎01-28-2016 02:22 AM
868 Views
michael_th
Contributor I

Hello Carlos,

I don't think that we have an FAE helping us.

I finally managed to install the unit test package for v4l2. I can now display what the adv7182 sends to the imx6 directly to the framebuffer, with this command :

root@BUI270:/home/appdata/unit_tests# ./mxc_v4l2_overlay.out -iw 800 -ih 480 -it

0 -il 0 -ow 720 -oh 625 -ot 0 -ol 0 -r 0 -t 50 -do 0 -fg -fr 30

g_display_width = 720, g_display_height = 625

g_display_top = 0, g_display_left = 0

[  824.077443] Powering on adv7182

sensor chip is adv7180_decoder

sensor supported frame size:

frame_rate is 30

[  824.098310] Powering on adv7182

frame buffer width 0, height 0, bytesperline 0

[  824.123309] imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_5 = 0x00000001

I can then see a black screen with a lot of white stripes for a few seconds. Afterwards, the screen becomes blue.

I suppose the adv7182 Doesn't lock to the video signal and goes in freerun mode.

The other problem is that i see some green random lines on the screen (also when it is in freerun mode), so I think i also have a clock or sync issue.

What I don't understand is why my cvbs signal doesn't get locked. I re-checked the pcb and the way the single ended CVBS signal is connected to the adv7182 is following the recommendations. I tried both with and without fast switch mode, without seeing any changes. I checked the camera and it is working, I see the cvbs signal on the oscilloscope.

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‎02-04-2016 09:14 AM
868 Views
CarlosCasillas
NXP Employee
NXP Employee

Hi Michael,

According with AE team, it seems that it is required to go back and revisit the modified driver. It seems to be missing some of the V4L IOCTLs (from the mxc_v4l2_capture log in this thread), and may not be programming some registers correctly.

The ADV7180 and ADV7182 are not software compatible, and have several register differences by what could be read in ANALOG's datasheets. Add to that it looks as if some of the IOCTLs needed for V4L are either deleted or non-functional.


Hope this will be useful for you.
Best regards!
/Carlos

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‎02-05-2016 02:33 AM
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michael_th
Contributor I

Hello Carlos,

Indeed something was wrong with the register values. It almost works now.

In adv7180_hard_reset I've entered different register settings. I found the information on the adv7182 datasheet.

The problem that i have now is that the first one or two times I see only horizontal stripes when i start the mxc_v4l2_overlay.out tool. After restarting a few times the tool I'm seeing a correct picture. I've also got this warning : imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_5 = 0x00000001

Here is the modified adv7180_hard_reset function in the adv7180 driver ( I could only test the single ended cvbs input) :

#define INPUT_FORMAT_SE_CVBS

#define SE_CVBS_INPUT_AN 3 //AN can be 1, 2, 3 or 4

//#define INPUT_FORMAT_YC

//#define YC_Y_AN1_C_AN2 //chose between those 2

//#define YC_Y_AN3_C_AN4 //

//#define INPUT_FORMAT_DIFF_CVBS

//#define DIFF_CVBS_P_AN1_N_AN2 //chose between those 2

//#define DIFF_CVBS_P_AN3_N_AN4

//#define INPUT_FORMAT_YPBPR

//#define FAST_SWITCH_MODE // fast switch mode for cvbs or differencial cvbs

//#define CHROMA_SHAPING_FILTER_MODE // chroma shaping filter mode for cbvs and differential cvbs

//#define FREE_RUN_MODE // chip outputs video signals without being connected to a source

static void adv7180_hard_reset(bool cvbs)

{

    dev_dbg(&adv7180_data.sen.i2c_client->dev,

        "In adv7180:adv7180_hard_reset\n");

    /*reset adv7180 */

    adv7180_write_reg(0x0f, 0x80);

    msleep(10);

    /* exit power down mode */

    adv7180_write_reg(0x0f, 0x00);

    /*Analog front end IBIAS settings */

#ifdef INPUT_FORMAT_DIFF_CVBS

    adv7180_write_reg(0x52, 0xC0); // input format Differential CVBS

#endif

#ifdef INPUT_FORMAT_SE_CVBS

    adv7180_write_reg(0x52, 0xCD); // input format Single Ended CVBS

#endif

#ifdef INPUT_FORMAT_YC

    adv7180_write_reg(0x53, 0xCE); // input format YC

#endif

#ifdef INPUT_FORMAT_YPBPR

    adv7180_write_reg(0x54, 0xC0); // input format YPbPr

#endif

    /* input select */

    /*Differential CVBS */

#ifdef INPUT_FORMAT_DIFF_CVBS

#ifdef DIFF_CVBS_P_AN1_N_AN2

    adv7180_write_reg(0x00, 0x8);

#endif

#ifdef  DIFF_CVBS_P_AN3_N_AN4

    adv7180_write_reg(0x00, 0x0f);

#endif

#endif

    /* Single Ended CVBS */

#ifdef INPUT_FORMAT_SE_CVBS

    adv7180_write_reg(0x00, SE_CVBS_INPUT_AN -1);

#endif

    /* YC */

#ifdef INPUT_FORMAT_YC

#ifdef YC_Y_AN1_C_AN2

    adv7180_write_reg(0x00, 0x8);

#endif

#ifdef YC_Y_AN3_C_AN4

    adv7180_write_reg(0x00, 0x9);

#endif

#endif

    /* YPbPr */

#ifdef INPUT_FORMAT_YPBPR

    adv7180_write_reg(0x00, 0xC);

#endif

    /* current clamp reset */

    adv7180_write_reg(0x0E, 0x80);

    adv7180_write_reg(0x9C, 0x00);

    adv7180_write_reg(0x9C, 0xFF);

    adv7180_write_reg(0x0E, 0x00);

   

    adv7180_write_reg(0x17, 0x41);

   

    /*differencial cvbs writes */

#ifdef INPUT_FORMAT_DIFF_CVBS

    /* common mode clamp setup */

    adv7180_write_reg(0x5A, 0x90);

    adv7180_write_reg(0x60, 0xA0);

    msleep(25);

    adv7180_write_reg(0x60, 0xB0);

    /*differencial analog front end setup */

    adv7180_write_reg(0x5F, 0xA8);

    adv7180_write_reg(0x0E, 0x80);

    adv7180_write_reg(0xB6, 0x08);

    adv7180_write_reg(0xC0, 0xA0);

    adv7180_write_reg(0x0E, 0x00);

#endif

#if  defined ( INPUT_FORMAT_DIFF_CVBS ) ||  defined ( INPUT_FORMAT_SE_CVBS )

#ifdef FAST_SWITCH_MODE

    adv7180_write_reg(0x0E, 0x80);

    adv7180_write_reg(0xD9, 0x44);

    adv7180_write_reg(0x0E, 0x40);

    adv7180_write_reg(0x0E, 0x01);

    adv7180_write_reg(0x0E, 0x00);

#endif

#ifdef CHROMA_SHAPING_FILTER_MODE

    adv7180_write_reg(0x17, 0x41);

#endif

#endif

    /* power up digital output pads */

    adv7180_write_reg(0x03, 0x0C);

    adv7180_write_reg(0x04, 0x07);

    /*crystal for osc input */

    adv7180_write_reg(0x13, 0x0);   

    /* power up digital output pads */

    adv7180_write_reg(0x1D, 0x40);

#ifdef FREE_RUN_MODE

    adv7180_write_reg(0x00, 0x05); // Adjust INSEL

    adv7180_write_reg(0x0C, 0x37); //Force Free-Run mode

    adv7180_write_reg(0x14, 0x11 ); //Set Free-Run : 100% color bars

#endif

}

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