i.MX6SDL CLKO tolerance.

[satoshishimoda]

Hi community,

I have a question about i.MX6SDL CCM.

I want to know the tolerance of CLKO (CLKO1, CLKO2) in the each case of following.

[Case 1]

Select osc_clk as CLKO source.

And CLKx_DIV is set to 000b (divide by 1).

[Case 2]

Select osc_clk as CLKO source.

And CLKx_DIV is set to other than 000b.

[Case 3]

Select xxx_clk_root that passes through PLL as CLKO source.

And CLKx_DIV is set to 000b (divide by 1).

[Case 4]

Select xxx_clk_root that passes through PLL as CLKO source.

And CLKx_DIV is set to other than 000b.

Best Regards,

Satoshi Shimoda

[art]

Do you mean the CLK1_P/N and CLK2_P/N differential clock outputs? If so, first, please refer to the Table 3 of the i.MX6SDL Data Sheet Rev.5 document. It says that these clock outputs "are LVDS differential pairs compatible with TIA/EIA-644 standard". According to that, please refer to the Section 4.7.3 of the same document for the AC parameters of these signals.

Have a great day,
Artur

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[satoshishimoda]

Hi Artur,

> Do you mean the CLK1_P/N and CLK2_P/N differential clock outputs?

Unfortunately, no.

I mentioned CLKO in sect. 18.6.21 in IMX6SDRM Rev.2.

According to this sect., CLKx_P/N is not selectable to use CLKO, so I feel the spec you mentioned is not apply to CLKO.

Best Regards,

Satoshi Shimoda

[art]

According to the Table 18-2 of the IMX6SDLRM Rev.2 document, the CCM_CLKO1 and CCM_CLKO2 signals are routed out of the chip as regular GPIO signals. So, according to that, please refer to the Section 4.7.1 "General Purpose I/O AC Parameters" of the i.MX6SDL Data Sheet Rev.5 document for the AC parameters of these signals.

Best Regards,

Artur

[sribinkr]

hii,

   pls give me suggestions on how i can give 800khz clock to an external chip through imx6q sabre lite board