AnsweredAssumed Answered

how to modify the norFlash size in boot start code?

Question asked by yang yang on Jan 20, 2016
Latest reply on Feb 2, 2016 by yang yang

ENV:

P2041e + NOR fLASH 128MB

 

mem:

0xFE00_0000 |  16MB | 0xFEFF_FFFF | CCSBAR

0xe800_0000 |  128MB | 0xeFFF_FFFF | NOR FLASH

 

1. when I edit the romInit.s, the system cannot be boot.

 

2. if I use the 0xff00_0000 |  16MB | 0xfFFF_FFFF | NOR FLASH cfg, in the romInit.s, then the system can be boot,  the ppc boot address must be 0xffff_fffc, so I think the norFLash address should be 0xf800_0000~0xffff_ffff, so I must move the CCSRBAR address.

 

would you please give me some suggestion?  I want to use the 128MB norFlash as the boot flash.

 

Try my best to modify the CCSRBAR address, but no useless, i donot know the reason.

the CCSBAR_RESET is 0xfe000000, the CCSBAR is 0xf0000000, I want to move the ccsrbar address space ,So  I could use the 0xf800_0000~0xffff_ffff as to the nor flash address.

the code as follows:

WRITEADR(r6,r7,P2041_LAWBARL7(CCSBAR_RESET),CCSBAR)

    WRITEADR(r6,r7,P2041_LAWAR7(CCSBAR_RESET),

   LAWAR_ENABLE | LAWAR_TGTIF_RESERVE | LAWAR_SIZE_16MB )

    LOADVAR(r7, P4080_LAWAR8(CCSBAR_RESET))

    isync 

 

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

    lwz     r4, (CCSRBARH_OFFSET)(r7)

 

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

    lwz     r4, (CCSRBARL_OFFSET)(r7)

 

    lis     r6,HI(CCSBAR)

    ori     r6,r6, LO(CCSBAR)

 

    xor     r5,r5,r5

    lis     r7,HI(CCSBAR_RESET)

    ori     r7,r7,LO(CCSBAR_RESET)

 

    stw     r5,(CCSRBARH_OFFSET)(r7)

    stw     r6,(CCSRBARL_OFFSET)(r7)

    sync

 

    lis     r5,HI(CCSBAR_COMMIT)

    ori     r5,r5, LO(CCSBAR_COMMIT)

    stw     r5,(CCSRAR_OFFSET)(r7)

    sync

 

    WRITEADR(r6,r7,P2041_LAWBARL7 (CCSBAR),0x0)

    sync

    WRITEADR(r6,r7,P2041_LAWAR7 (CCSBAR),0x0)

    LOADVAR(r7, P2041_LAWAR7 (CCSBAR))

    isync  

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