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Configure OSC1 as EXTAL ref for PLL0 and PLL1

Question asked by Ramesh Goud on Jan 19, 2016
Latest reply on Feb 4, 2016 by Kerry Zhou

Hi,

     Am using 12 Mhz crystal as my External reference clock which is OSC1 and another high range crystal is using as OSC0, I want the configurations for PLL0 and PLL1 which are using the EXTAL as OSC1 only.  

 

  Here am sharing my code snippet for configuring MCG and DDR

 

MCG:

  /* Generate a reset request on a loss of OSC1 external reference clock and High frequency range selected for the crystal oscillator  */

    temp8 =  ESAL_GE_MEM_READ8(MCG_C10);

    temp8 &= ~(0x30 | 0x8 | 0x4);

    temp8 |= (1<<4 | 0 << 3 | 0 << 2);

    ESAL_GE_MEM_WRITE8(MCG_C10, temp8);

 

 

    /* External reference clock is selected and write frdiv (5) value */

    temp8 =  ESAL_GE_MEM_READ8(MCG_C1);

    temp8 &= ~(0x4 | 0x38 | 0xc0);

    temp8 = 2<<6 | frdiv<<3;

    ESAL_GE_MEM_WRITE8(MCG_C1, temp8);

 

    /* Wait until clock is stable */

    for(temp32=0;temp32<100000;temp32++);

 

    /* FBE Mode */

    /* External clock monitor is disabled for OSC1  */

    ESAL_GE_MEM_WRITE8(MCG_C12, ESAL_GE_MEM_READ8(MCG_C12) | MCG_C12_CME);                    ( MCG_C12_CME => 0x20 )

 

    /* PLL0, OSC1 is selected as the reference clock */

    ESAL_GE_MEM_WRITE8(MCG_C5, ESAL_GE_MEM_READ8(MCG_C5) | (MCG_C5_PLLREFSEL));          (  MCG_C5_PLLREFSEL => 0x80 )

 

    /* Select PLL0 as the source of the PLLS mux (PLLCS filed)  */

    ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) & (~MCG_C11_PLLCS));          (MCG_C11_PLLCS => 0x10 )

 

    /* Set PRDIV0 value */

    temp8 = ESAL_GE_MEM_READ8(MCG_C5);

    temp8 &= ~MCG_C5_PRDIV;

    temp8 |= (prdiv_val - 1);

    ESAL_GE_MEM_WRITE8(MCG_C5, temp8);

 

    /* Set PLLS bit and VDIV0 values */

    temp8 = ESAL_GE_MEM_READ8(MCG_C6);

    temp8 &= ~MCG_C6_VDIV;

    temp8 |= MCG_C6_PLLS | (vdiv_val - 16);

    ESAL_GE_MEM_WRITE8(MCG_C6, temp8);

 

   /* Wait for PLLST status bit to set */   

    for(temp32=0;temp32<100000;temp32++); 

 

    /* PBE Mode */

    /* Output of FLL or PLLCS is selected (depends on PLLS control bit) */

    ESAL_GE_MEM_WRITE8(MCG_C1, ESAL_GE_MEM_READ8(MCG_C1) & (~MCG_C1_CLKS));              ( MCG_C1_CLKS => 0xc0 )

 

    /* Wait for clock status bits to update */

    for(temp32=0;temp32<100000;temp32++); 

 

DDR:

 

    ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) | (MCG_C11_PLLREFSEL2));    (MCG_C11_PLLREFSEL2 => 0x80)

 

    /* Set PRDIV1 value */

    temp8 = ESAL_GE_MEM_READ8(MCG_C11);

    temp8 &= ~MCG_C11_PRDIV1;                               (MCG_C11_PRDIV1 => 7)

    temp8 |= (prdiv_val - 1);                                           (prdiv_val => 5)

    ESAL_GE_MEM_WRITE8(MCG_C11, temp8);

 

 

    /* Set VDIV1 value (Divide Factor is 30-16 = 14) */

    temp8 = ESAL_GE_MEM_READ8(MCG_C12);

    temp8 &= ~MCG_C12_VDIV1;                                  ( MCG_C12_VDIV1 => 0x1F)

    temp8 |=  (vdiv_val - 16);                                             (vdiv_val => 30)

    ESAL_GE_MEM_WRITE8(MCG_C12, temp8);

 

 

    /* Now enable the PLL clock */

    ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) | (MCG_C11_PLLCLKEN2));  (MCG_C11_PLLCLKEN2 => 0x40 )

 

 

    /* Wait for LOCK bit to set */

    for(temp32=0;temp32<100000;temp32++);

 

when i configure the Register MCG_C12 to enable the clock monitor for OSC1, It's throwing the error as unable to read the RAM.

help me on the above...

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