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MPC5200B SDRAM_CLK_EN pin

Question asked by Patrick Gillespie on Jan 18, 2016

According to appnote AN3221, "CKE is automatically held at logic low until the DRAM controller is enabled." Additionally, "CKE will automatically be brought high when SDRAM is enabled." 

Several questions about this:

(1) Is this meant to imply that there is no ability to control CKE prior to the SDRAM controller being enabled?

(2) At what point is the SDRAM controller considered to be enabled?   I can find no SDRAM controller enable bit.

(3) Is the automatic behavior not overriden by writes to the Control Register  at MBA + 0x0104, accessing bit 1, the CKE bit?

 

I have an SDRAM I wish to use that requires CKE to be high rather than low during the initial 100uS delay period.

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