In the "i.MX 6 Series DDR Calibration" document page 34,
the sample code enables power mode at the end of the calibration.
// enable Adopt power down timer:
reg32_write((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET),
reg32_read((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)) & 0xfffffff7)
This code is trying to unmask bit 3 in MMDC0_MAPSR, however in the RM page 3927, the bit 3 is a reserved bit.
Is it actually 0xfffffffe to set 0 in the bit 0?