this question relates to other one solved already several months ago by us with use of LS1021A silicon rev 1.x:
As we moved with our design and put LS1021A rev. 2.0 to our custom board, we have noticed changes in processor behavior. The 25-bit IFC mode for CS0 seems not working anymore.
This is our setup:
1. We use custom board with LS1021A silicon rev 2.0
2. We use BDI3000 for initial board bring-up
3. Using BDI tool we are able to provide hard-coded RCW to the processor and make it coming out of reset, that is we are able to get to BDI CLI and read processor registers, we can even access DDR after configuring it in BDI configuration file.
4. But we are not able to communicate with NOR flash in 25-bit IFC mode (the BDI configuration is correct and same as for previous design) - the measurements made with use of scope show, that access on the IFC bus is forced by the processor somehow to be 28-bit
5. how we initially program NOR:
a. We are overwriting hard-coded RCW via JTag
b. We are providing appropriate RCW source externally by CPLD (25-bit IFC mode, 16-bit nor flash etc.)
c. We are configuring IFC CS0 in BDI configuration file for correct CS addressing and timings
d. This setup works well with earlier processor revision and we can easily program NOR flash with RCW, bootloader etc. but this does not work with latest processor rev 2.0
Any response would be appreciated much.