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Interfacing P4080 SoC with Virtex 5 FPGA

Question asked by Drew Boudreau on Jan 14, 2016
Latest reply on Jan 14, 2016 by Pavel Chubakov

We currently have a simple setup of a P4080 SBC cabled to a MMPlus baseboard and V5 (70T, -2) mezzanine card.  The MMPlus baseboard has a CX4 connector that we have cabled to the SBC.  We are operating at 2.5GHz (tried at 3.125 also).  Loopback (in cables) to the CX4 connector works well, tested using SRA application and ported code from an MPC8548E.  Loopback also works in the entire cable chain from the Virtex 5 FPGA (V5).  When the two are connected we are seeing a lot of disparity and notintable (8b/10b encoder table) errors on the RX side of the V5.  Are there any known issues when using a cabled SRIO setup that I have described?  Has anyone else tried connecting these two devices?

 

I initially thought there was only a signal integrity component to our issues but since Bit Error Rate tests and SRIO loopback all work, through twice the length of cable, I do not suspect this is the sole issue.  

 

We do see IDLE sequences come through on the V5, but only a few cycles until the rxdata is filled with garbage. 

 

Thank you for the help!

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