Setting for DDR3 Double Refresh in the iMX6 at high temps

[victordamptey]

Any ideas on how to increase DDR3 refresh rate based on high temp or how to set in IVT  as a default?

Thanks

[Yuri]

Hello,

  DRAM refresh options may be configured via MMDC Core Refresh Control Register

during memory initialization (in U-boot DCD table) ; please use section 44.12.9

(MMDC Core Refresh Control Register (MMDCx_MDREF) the i.MX6 D/Q Reference Manual

(IMX6DQRM, Rev. 3, 07/2015) for more details.

  As for LPDDR2, please refer to section 44.8 ( LPDDR2 Refresh Rate Update

and Timing Derating) of the i.MX6 RM.

Also, please use section 44.4.8 (Refresh Scheme) of the i.MX6 RM.

Have a great day,
Yuri

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[victordamptey]

Hi Yuri,

Thanks for the information. In order to avoid reinventing the wheel, is the

code that does this somewhere? Maybe in Freescale manufacturing tool or

elsewhere.

Thanks

Swtrktr

[Yuri]

Please look at section 4 (CUSTOMIZING BOARD CODE)

ofU-Boot Migration Example​  about DCD.

MMDC0_MDREF has address 0x021b0020

originally it may contain somewhat similar to  0x00005800.

It is needed to change line with MMDC0_MDREF address.

Regards,

Yuri.

[victordamptey]

Thanks.