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P1021-QE Processor's UCC Bit shifting problem in NMSI mode

Question asked by Amanaganti VinodKumar on Jan 12, 2016
Latest reply on Jan 20, 2016 by Amanaganti VinodKumar

Hi All,

 

I am working on P1021rdb board, we are using NMSI mode for Custom protocol implementation. We are successfully put the UCC in fast protocol with transparent mode and using NMSI configuration.

 

We are trying Processor's pin level loopback.

As mentioned in the QE-data sheet (page 7-13 and page 7-14) NMSI and Transparent

cdp = 0

ctsp = 0

cds = x ( app specific)

ctss = x (app specific)

 

We set cdp, ctsp to zero and set ctss = 1.

 

case-1)

cds = 0, in this case sometimes we are able get the proper data (data received is matched with the data that is sent) in pin level loopback. But sometimes we are observing 1 bit shifting in the received data stream.

 

case-2)

cds =1, in this case always there is a bit shift and none of the times we received data properly.

 

We have gone through the datasheet from the timing diagrams mentioned in

6.5 Controlling UCC Timing with the RTS, CTS, and CD Signals

We understand following points

1) All control signals (RTS, CTS, and CD) are asserted on falling edge of the clock

2) Data is sent and received on falling edge of the clock only.

3) if CDS = 0, before receiving data CD must be sampled on raising edge of the clock

 

In our testing regardless of CTS, CD status data is sent and received. Could you please guide us how we can overcome the 1-bit shifting issue. 

unlike TDM there is no option like clock edge selection configuration for sending receiving data, How usually NMSI mode is configured to avoid these bit shifting issues

Your help is appreciated.

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