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Is there some restriction for i.MX6DQ ESAI bit-clock?

Question asked by Satoshi Shimoda on Jan 6, 2016
Latest reply on Jan 20, 2016 by Yuri Muhin

Hi community,

 

I have a question about i.MX6DQ ESAI.

At first, please see Chapter 61.8.4.2 in IMX6DQRM Rev.3.

It shows about the restriction to set bit-clock frequency and register setting (DIV2, PSR and PM) for SSI in the NOTE.

I want to know whether ESAI has similar restriction or not.

I found the restriction when using exterrnal ESAI serial clock in the NOTE of Table 25-3.

But I did not find any restriction when using internal clock.

So I understand ESAI has no restriction for bit-clock frequency and register setting when using internal clock (Fsys or EXTAL) to its clock source.

In other words, I can set TPSR=1b, TPM=0x00, and TFP=0x0 in ESAI_TCCR register at the same time.

Is my understanding correct?

 

 

Best Regards,

Satoshi Shimoda

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