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MPC5748G 9 bit frame uart mode

Question asked by Brad Stewart Employee on Jan 5, 2016
Latest reply on Jan 7, 2016 by Lukas Zadrapa

Issue:  9-bit frames with MPC5748G solution or work-around?

Message from customer below

--Brad

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In some of our communications using the MC9S12XDP512 processor we use the 9-bit frames of the UART for RS-485 communications.  Below is some documentation regarding this feature for the MC9SXDP512 processor.  In 9-bit frame mode the 9th bit can be configured as a parity bit or data bit.  There are registers that can be accessed for the transmit and receive of the 9th bit that are easy to access by software.

 

In porting the software from the MC9S12XDP512 processor to the new MPC5748G processor the documentation for the MPC5748G states that the core supports 9-bit frames, but then states that the ninth bit should be a parity bit (page 1931 of the MPC5748GRM.pdf, version 4 document).

 

 

Question:  When sending data, it is possible to force a bit of 0 or 1 for the parity bit through the PC[1:0] bits of the LINFlexDx_UARTCR register; however this requires going into initialization mode which is in a different register for changing the UART bit value every time the bit needs to be changed for transmitting data.  Below are the control bits of the LINFlexDx_UARTCR register for setting the 9th bit value.

 

 

In regards to receiving data from the UART for 9 bit frames there doesn’t seem to be anyway to examine the bit value of the parity bit (9th bit) but in the MC9S12XDP512 processor one can.  The LINFlexDx_UARTSR has the PE bit flags that indicate a parity error for received data.  It would be helpful if these bits could be configured to give the 9th bit value instead, perhaps.

 

For such a high powered processor I’m a bit surprised that the parity bit cannot be used as a data bit in 9-bit frames.    Freescale processors supported this feature in the past and so do other chip manufactures as well.

 

For our purposes I think we can make the current UART hardware for the MPC5748G processor work for our application, but I wanted to comment to NXP about this issue as this core is really impressive.

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